Abstract: A nonwoven fabric web having an excellent sound absorption coefficient in a frequency range from 800 Hz to 1000 Hz when used as a sound absorbing member for a vehicle exterior. The nonwoven fabric web including a nonwoven fabric having meltblown fibers and binder fibers arranged so as to be confounded with the meltblown fibers and fused with the meltblown fibers at some of the confounding points at the very least, the weight per unit area of the nonwoven fabric being from 400 g/m2 to 1500 g/m2, and the flexural rigidity of the nonwoven fabric being from 2.0 N/50 mm to 20.0 N/50 mm.

Abstract: A nonwoven fabric web having an excellent sound absorption coefficient in a frequency range from 800 Hz to 1000 Hz when used as a sound absorbing member for a vehicle exterior. The nonwoven fabric web including a nonwoven fabric having meltblown fibers and binder fibers arranged so as to be confounded with the meltblown fibers and fused with the meltblown fibers at some of the confounding points at the very least, the weight per unit area of the nonwoven fabric being from 400 g/m2 to 1500 g/m2, and the flexural rigidity of the nonwoven fabric being from 2.0 N/50 mm to 20.0 N/50 mm.

Abstract: Design time (TAT) is reduced in a layout design of a semiconductor integrated circuit having a well supplied with a potential different from a substrate potential. A layout design method of the present invention includes preparing a first cell pattern placed on a semiconductor substrate of a first conductive type, preparing a second cell pattern having a deep well of a second conductive type, placing the first cell pattern in a first circuit region, and placing the second cell pattern in a second region different from the first circuit region. This reduces TAT in chip design.

Abstract: A method of forming a semiconductor integrated circuit, includes providing a first logic cell, a second logic cell and a metallic wiring connected to the first logic cell and a gate electrode of the second logic cell, and providing a third logic cell including a gate electrode connected to the metallic wiring, such that the third logic cell makes no contribution to a logic operation of the semiconductor integrated circuit, in order that an antenna ratio of the first gate electrode to the metallic wiring does not satisfy an antenna criterion, and an antenna ratio of the first gate electrode and the second gate electrode to the metallic wiring satisfies the antenna criterion.

Abstract: Design time (TAT) is reduced in a layout design of a semiconductor integrated circuit having a well supplied with a potential different from a substrate potential. A layout design method of the present invention includes preparing a first cell pattern placed on a semiconductor substrate of a first conductive type, preparing a second cell pattern having a deep well of a second conductive type, placing the first cell pattern in a first circuit region, and placing the second cell pattern in a second region different from the first circuit region. This reduces TAT in chip design.

Abstract: Design time (TAT) is reduced in a layout design of a semiconductor integrated circuit having a well supplied with a potential different from a substrate potential. A layout design method of the present invention includes preparing a first cell pattern placed on a semiconductor substrate of a first conductive type, preparing a second cell pattern having a deep well of a second conductive type, placing the first cell pattern in a first circuit region, and placing the second cell pattern in a second region different from the first circuit region. This reduces TAT in chip design.

Abstract: In a semiconductor integrated circuit, a cell arrangement area is provided on a semiconductor substrate to allow a plurality of basis cells to be arranged. A basic power supply line is provided in an upper layer than the cell arrangement area to supply a power. A switch cell is configured to control the power supply from the basic power supply line to an inside of the cell arrangement area. An always operating cell is arranged in the cell arrangement area adjacently to the switch cell, and is configured to receive the power from the switch cell even when the switch cell stops the power supply to the cell arrangement area.

Abstract: A method of supporting design of a semiconductor integrated circuit, is achieved by generating a data indicating a basic cell and a data indicating a cell group different in logic from the basic cell; and by storing the basic cell indicating data and the cell group indicating data in a library of a storage unit. An outer shape and a position of a wiring pattern of the cell group are same as those of the basic cell. The wiring pattern of the basic cell and the wiring pattern of the cell group contain a wiring obstruction section indicating an area in which a passage wiring is inhibited. When a design change is carried out, the basic cell is replaced by a change cell of the cell group corresponding to the design change.

Abstract: A method of designing a semiconductor integrated circuit, includes verifying an antenna ratio of a metallic wiring connected to a first gate electrode and the first gate electrode, based on a layout information, and computing a gate area that should be added to avoid a plasma damage to the first gate electrode, based on the verifying. The method further includes modifying a layout of the semiconductor integrated circuit, based on the computing, by arranging a logic cell having a second gate electrode having the gate area or more and is in a state where the logic cell makes no contribution to a logic operation of the semiconductor integrated circuit, in a free region of the layout, and connecting the second gate electrode to the metallic wiring.

Abstract: In a semiconductor integrated circuit, a cell arrangement area is provided on a semiconductor substrate to allow a plurality of basis cells to be arranged. A basic power supply line is provided in an upper layer than the cell arrangement area to supply a power. A switch cell is configured to control the power supply from the basic power supply line to an inside of the cell arrangement area. An always operating cell is arranged in the cell arrangement area adjacently to the switch cell, and is configured to receive the power from the switch cell even when the switch cell stops the power supply to the cell arrangement area.

Abstract: Design time (TAT) is reduced in a layout design of a semiconductor integrated circuit having a well supplied with a potential different from a substrate potential. A layout design method of the present invention includes preparing a first cell pattern placed on a semiconductor substrate of a first conductive type, preparing a second cell pattern having a deep well of a second conductive type, placing the first cell pattern in a first circuit region, and placing the second cell pattern in a second region different from the first circuit region. This reduces TAT in chip design.

Abstract: A sequence control apparatus includes a control unit and a memory unit detachably mounted to the control unit. The memory unit includes a memory device connected to an input circuit and an output circuit of the control unit via a pin connector. The memory device itself conducts logical operations in response to the input signals applied to the input circuit of the control unit.

Abstract: An electronic timer wherein a counting circuit for counting outputs of a CR oscillating circuit comprises a plurality of partial counting circuits which are cascade-connected with one another, the respective partial counting circuits are automatically reset by an automatic resetting circuit when a source current voltage is applied or reset by an external resetting circuit at a desired time, the outputs of the CR oscillating circuit are counted by the respective partial counting circuits after the resetting, and a following output circuit is driven when the count reaches an externally set value of a setting circuit. The partial counting circuits are divided into groups by an external driving test circuit to quickly test the operation of the counting circuit.

Abstract: Contactless two-line type timer circuit operable stably for a load of even a small current. In the circuit comprising substantially a full-wave rectifying circuit connected through the load to AC source, a thyristor connected across output terminals of the rectifying circuit and means for applying pulses to the gate of the thyristor after a predetermined time period, a first resistance is inserted between the cathode of the thyristor and negative side output terminal of the rectifying circuit and a second resistance is inserted between the gate of the thyristor and said negative side output terminal so as to allow the thyristor to be of a lower gate sensitivity and to be capable of keeping the gate voltage of the thyristor always larger than the cathode voltage.