Abstract: A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.

Abstract: A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.

Abstract: A semiconductor device includes a first memory controller configured to output a first control signal to first and second external memories through a first memory interface, a second memory controller configured to output a second control signal to the second external memory through a second memory interface, an inter-device interface for communicating with another semiconductor device, terminals configured to output the second control signal that has passed through the second memory interface, and a first selector configured to select between the second memory interface and the inter-device interface in accordance with an operation mode of the semiconductor device and to couple the selected interface to the terminals.

Abstract: A storage device holds data and error correcting codes. An LUT stores a relation between a memory address and an error correction level. An error detection level processing unit calculates, based on an access address included in an access instruction to the storage device and the LUT, the error correction level corresponding to the access address. The write controller calculates an error correcting code based on the error correction level that is calculated, and writes the error correcting code together with data in the storage device. A read controller performs error correction processing using the error correcting code based on the error correction level that is calculated, to supply data after error correction.

Abstract: Image data storage areas of a plurality of pages are allocated for each of a plurality of display planes capable of superimposed display, and display output processing is performed while switching between the image data storage areas is being performed for each display plane. In such a display system, versatile switching between image data storage areas is enabled without heavily loading a central processing unit. Attribute bits of a TRAP command indicating the termination of drawing of one display plane are provided with display switching enable bits indicating whether to perform switching between image data storage areas for each display plane. For display planes corresponding to the display switching enable bits of “1”, switching to an image data storage area from which image data is read is performed at timing synchronous with a next vertical synchronous signal.

Abstract: Image data storage areas of a plurality of pages are allocated for each of a plurality of display planes capable of superimposed display, and display output processing is performed while switching between the image data storage areas is being performed for each display plane. In such a display system, versatile switching between image data storage areas is enabled without heavily loading a central processing unit. Attribute bits of a TRAP command indicating the termination of drawing of one display plane are provided with display switching enable bits indicating whether to perform switching between image data storage areas for each display plane. For display planes corresponding to the display switching enable bits of “1”, switching to an image data storage area from which image data is read is performed at timing synchronous with a next vertical synchronous signal.

Abstract: A semiconductor device is connected to a CPU, a memory and I/O devices to serve as a data transfer bridge for efficient data transfer between the memory and the I/O devices. A CPU interface and a plurality of I/O interfaces included in a bridge chip are connected through an internal bus to a memory interface included in the bridge chip. Each I/O interface has a read/write buffer and a DMAC. An arbiter included in the bridge chip determines a bus master for which data transfer is permitted in response to requests for data transfer from each of the CPU interface and the DMAC to the memory. Each of the I/O interfaces has a control function to skip part of areas in the memory when transferring data between the memory and the I/O interface.

Abstract: In a system that decompresses data compressed in compliance with the MPEG or JPEG standard, a buffer memory (603) to store values computed during decompression of the compressed data is split to plural banks (BNK); each of the banks is provided with an all-zero flag (AZF) indicating whether data within the bank is all “0”s; when data to be written to a bank is all “0”s, the all-zero flag is set without performing actual writing to the buffer memory; and during data reading, the flag is sensed to see if data within the bank is all “0”s, at which time reading from the buffer memory is omitted.

Abstract: An image processor which is connected to a system bus that connects a processor for forming graphic command related to image processing to a main memory that holds command and original image data, and draws image on the frame buffer based upon said graphic command from said processor, wherein said graphic processor has a data bus change-over unit which connects said system bus to a first data bus that is connected to a graphic data memory holding said graphic command and said original image data, or connects said first data bus to a frame buffer which holds the data to be displayed. The image processor realizes a high-speed processing at a reduced cost by using a graphic memory bus coupled to a graphic processor.