Abstract: An object of the present invention is to perform long-distance TCP/IP transfer at a high throughput and in a short period of time. According to the present invention, in a communication system in which transmission data is transferred using a transmission-side TCP device and a receiving-side TCP device, the transmission-side TCP device includes a plurality of first IP processing units, a plurality of first TCP processing units, a plurality of compression processing units, a plurality of second TCP processing units, and a plurality of second IP processing units. The receiving-side TCP device includes a plurality of third IP processing units, a plurality of third TCP processing units, a plurality of decompression processing units, a plurality of fourth TCP processing units, and a plurality of fourth IP processing units. The respective units perform processing independently of and in parallel with each other.

Abstract: To provide a packet processing device that prevents a reduction in the efficiency of data communication. A packet processing device 100 estimates a time, which is taken until an acknowledgement corresponding to a packet is received after transmitting the packet to a client 30, as the round-trip delay time of the packet, determines the size of data that is divided into packets and is continuously transmitted to the client 30, and updates the transmission rate of packets transmitted to the client 30 according to the data size and the round-trip delay time.

Abstract: To provide a packet processing device that prevents a reduction in the efficiency of data communication. A packet processing device 100 estimates a time, which is taken until an acknowledgement corresponding to a packet is received after transmitting the packet to a client 30, as the round-trip delay time of the packet, determines the size of data that is divided into packets and is continuously transmitted to the client 30, and updates the transmission rate of packets transmitted to the client 30 according to the data size and the round-trip delay time.

Abstract: A seat heater (10) that is provided on a seat (1) including a seat cushion (2) and a seat back (3) includes a first heating element (12U) provided in an upper section (3Lu) of a backrest (3L) in the seat back (3) and a second heating element (12L) provided in a lower section (3Ll) of the backrest (3L) in the seat back (3). In addition, a heat generation density of the first heating element (12U) is lower than a heat generation density of the second heating element (12L).

Abstract: A seat heater (10) that is provided on a seat (1) including a seat cushion (2) and a seat back (3) includes a first heating element (12U) provided in an upper section (3Lu) of a backrest (3L) in the seat back (3) and a second heating element (12L) provided in a lower section (3Ll) of the backrest (3L) in the seat back (3). In addition, a heat generation density of the first heating element (12U) is lower than a heat generation density of the second heating element (12L).

Abstract: A packet relaying apparatus which relays packets with a guaranteed bandwidth between terminals is comprised of a session control information analyzing section which identifies a required bandwidth required for a session to be established between the terminals by analyzing session control information contained in packets of control session protocols between the terminals, and a bandwidth correction section which corrects the identified required bandwidth based on the header size information of the packets, in order to guarantee the corrected bandwidth for the packets relating to the session.

Abstract: An electrically alterable non-volatile memory having a memory cell array including a plurality of memory cells, each memory cell including a transistor having a selected one of a plurality of different threshold voltages; a reference cell array including at least one set of reference cells, each reference cell in the set being set to a different threshold voltage; selection circuitry for selecting one of the memory cells; and a comparing circuitry for comparing a memory current read out of the selected memory cell with each of reference currents read out of the reference cells, sequentially in an order of levels of the threshold voltages set for the reference cells, respectively, thereby outputting data according to such comparison.

Abstract: A semiconductor device including a silicon substrate, an insulator film formed on said substrate, a transistor provided on said insulator film and a capacitor formed in a trench formed in said insulator film, and a method of manufacturing the same.

Abstract: A semiconductor memory device includes a dielectric layer formed on a conductive thin film layer constituting a shield electrode for effecting element separation in a field area, the dielectric layer connected to a dielectric layer of a capacitor with a lower electrode having part thereof opposite to part of the shield electrode through the dielectric layer, and has an increase in electrode area of a memory cell to be able to attain the high level of integration.

Abstract: A non-volatile semiconductor memory device capable of selectively storing one of at least three different data comprises a memory array including a plurality of memory cells, each having a control gate, a floating gate, a drain, and a source, a circuit for producing a stepped voltage whose level is varied stepwise to a number of different levels corresponding to a number of data to be stored, a circuit for producing a pulse voltage having a predetermined voltage level and a predetermined pulse width, and a circuit for selecting one of the plurality of memory cells, wherein during storing of the at least three different data the stepped voltage and the pulse voltage are applied to the control gate and the drain of the selected memory cell, respectively, while a timing of application of the pulse voltage to the drain is controlled relative to a timing of application of the stepped voltage to the control gate, depending on which of the at least three different data is to be stored into the selected memory cell.

Abstract: A method of using a non-volatile semiconductor memory comprising a plurality of row and column lines, a plurality of memory cells disposed at intersections of the row and column lines and a plurality of reference cells disposed on each of the row lines. Each memory cell includes an MOS transistor having a substrate, a spaced-apart drain and source formed on one surface of the substrate, a channel region between the drain and source and a lamination of a tunnel insulating film, a floating gate, an interlayer insulating film and a control gate formed in that order on the channel region.

Abstract: A semiconductor transistor device comprises a gate electrode disposed over an insulating surface, a spacer element located at the end of the gate electrode, a gate insulating film covering the gate electrode, a first diffusion region spaced apart from one end of the gate electrode, separated therefrom by the gate insulating film and by the spacer element which reduces the electric field between the gate and first diffusion region, the first diffusion region extending vertically above the gate insulating film, and a second diffusion region disposed above the gate insulating film having one end spaced from the first diffusion vertically extending region.

Abstract: A semiconductor memory device having memory cells including a transistor and a trench type capacitor which are formed on a semiconductor substrate to cooperate with each other to store information. The device includes a trench having a bottom made of a first insulator disposed on the semiconductor substrate and a sidewall made of an epitaxial semiconductor layer which is epitaxially grown on the semiconductor substrate in a substantially vertical direction around the first insulator. The capacitor comprises an impurity diffused layer formed on the sidewall of the trench, a second insulator layer formed over thee impurity diffused layer, and a conductive layer opposite of the impurity diffused layer via the second insulator layer, with the transistor formed on the epitaxial semiconductor layer.

Abstract: The edge of a 180.degree. phase shifter on a glass substrate of a reticle has a tapered structure, and a reduction of the intensity of transmitted light by an interference in the boundary area between the phase shifter and the glass substrate is moderated.

Abstract: A semiconductor memory device having transistors and capacitors on a semiconductor substrate with the lower electrodes and the contact holes for connection with the sources of the transistors formed on a self-alignment basis and a method of producing the same are disclosed. The transistor of the semiconductor memory device formed on the semiconductor substrate has a first insulating layer, a gate electrode, a source portion and a drain portion. The source and drain portions dispose in the vicinity of the gate electrode, on opposite sides of each other relative to the gate electrode, under the first insulating layer and in the semiconductor substrate.

Abstract: A semiconductor memory device having an excellent data holding characteristics because of a small leak current from a trench and a process for producing the same are disclosed. An SiO.sub.2 film 12 having an appropriate pattern is formed on a P type silicon substrate 11. Trenches 14 are relatively formed on the SiO.sub.2 film 12 by selectively growing a P type epitaxial layer 13 on the silicon substrate 11 using the SiO.sub.2 film 12 as a mask. An N type layer 23 acting as an electrode of a capacitor 27 is formed on the inner wall of the trench 14 by the oblique ion implantation of impurities 22 thereto. A polycrystalline silicon film 25 acting as an opposite electrode of the capacitor 27 is formed on an ONO film 24 so that the ONO film 24 is disposed between the polysilicon film 25 and the SiO.sub.2 film. The semiconductor memory device which is produced by this method without etching to form the trenches 14 has a fewer crystal defects in the epitaxial layer 13 around the trenches 14.

Abstract: A method of manufacturing a nonvolatile semiconductor memory including forming a first insulating film, a first semiconductor film for forming floating gates, a second insulating film, and a second semiconductor film for forming control gates in that order on a semiconductor substrate, and forming etching masks, each having a configuration corresponding to that of the floating gate, at every other one of areas on the second semiconductor film where the floating gates are to be formed. Side wall spacers are formed on both side walls of each of the etching masks and a third semiconductor film, formed of the same material as that of the second semiconductor film is selectively grown on parts of the second semiconductor film which are not covered by any of the etching masks and the side wall spacers.

Abstract: An MOS type semiconductor device having an SOI structure comprises an insulating film formed on a semiconductor substrate, a conductive layer formed on the insulating film serving as a gate electrode, a dielectric film covering upper and side surfaces of the conductive and the insulating film and a single semiconductor layer formed on the dielectric film, the semiconductor layer including a first part formed over an upper surface of the conductive layer, a second part formed on a side surface of the conductive layer and a third part formed over a part of the dielectric film covering directly the insulating film so that the first and third parts serve as a source and a drain or vice versa and the second part serves as a channel.

Abstract: Spherical fused silica with an average particle diameter within the range of 10 to 50 .mu.m and having a particle size distribution of 1 to 100 .mu.m in diameter is a useful filler for resin compositions having improved mechanical and electrical properties as well as good flowability and low viscosity. The spherical fused silica is preferably treated on its surface with a silane coupling agent. Resin compositions containing said spherical fused silica as the major filler are particularly useful as casting materials.

Abstract: One-component epoxy resin coating materials comprising(A) an epoxy resin or a mixture of epoxy resins,(B) as hardener for the epoxy resin at least one aromatic dicarboxylic acid dihydrazide or a triazine compound of the formula I ##STR1## (R=alkylamino or dialkylamino having 1 or 2 carbon atoms in the alkyl moieties, phenylamino or hydrazino) and(C) an anti-sagging agent or an inorganic filler or a mixture of anti-sagging agent and an inorganic filler, are used for the coating of fixed resistors. The resultant coatings exhibit good heat, moisture and cracking resistance.