Patents by Inventor Kenji Asaki
Kenji Asaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11709523Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.Type: GrantFiled: September 27, 2021Date of Patent: July 25, 2023Inventors: Kenji Asaki, Shuichi Tsukada
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Publication number: 20230078117Abstract: Apparatuses including and methods for memory subword driver circuits with reduced gate induced drain leakage are described. An example apparatus includes a first subword line and a second subword line coupled to the first subword line by a first common transistor where, in response to a test mode signal, a voltage of each of the first and second subword lines is raised to a first voltage and a gate voltage of the first common transistor is raised to a second voltage. In another example apparatus first and second subword drivers are coupled to the first and second subword lines respectively, and a driver circuit is coupled to the first and second subword drivers. The driver circuit outputs a first high signal to cause the first and second subword lines to rise to the first voltage and the gate voltage of the first common transistor to rise to the second voltage.Type: ApplicationFiled: September 14, 2021Publication date: March 16, 2023Applicant: MICRON TECHNOLOGY, INC.Inventor: Kenji Asaki
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Patent number: 11581032Abstract: An apparatus including a temperature dependent circuit is configured to receive a temperature dependent power supply voltage, and further is configured to receive a first input signal and provide a temperature dependent output signal responsive to the input signal. A power control circuit including the temperature dependent circuit is configured to receive a second input signal, and further configured provide a first control voltage based on the first temperature dependent output signal and provide a second control voltage based on the second input signal. The second control voltage has a temperature dependency based on the temperature dependent power supply voltage. A sense amplifier coupled to a pair of digit lines is configured to receive the first and second control voltages and amplify a voltage difference between the digit lines of the pair.Type: GrantFiled: April 20, 2021Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventor: Kenji Asaki
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Publication number: 20230019887Abstract: Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.Type: ApplicationFiled: September 28, 2022Publication date: January 19, 2023Applicant: MICRON TECHNOLOGY, INC.Inventors: Akira Yamashita, Kenji Asaki
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Publication number: 20220336007Abstract: An apparatus including a temperature dependent circuit is configured to receive a temperature dependent power supply voltage, and further is configured to receive a first input signal and provide a temperature dependent output signal responsive to the input signal. A power control circuit including the temperature dependent circuit is configured to receive a second input signal, and further configured provide a first control voltage based on the first temperature dependent output signal and provide a second control voltage based on the second input signal. The second control voltage has a temperature dependency based on the temperature dependent power supply voltage. A sense amplifier coupled to a pair of digit lines is configured to receive the first and second control voltages and amplify a voltage difference between the digit lines of the pair.Type: ApplicationFiled: April 20, 2021Publication date: October 20, 2022Applicant: MICRON TECHNOLOGY, INC.Inventor: Kenji Asaki
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Patent number: 11475939Abstract: Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.Type: GrantFiled: December 17, 2020Date of Patent: October 18, 2022Assignee: Micron Technology, Inc.Inventors: Akira Yamashita, Kenji Asaki
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Publication number: 20220199146Abstract: Apparatuses and methods for saving power at an input buffer are described. An example apparatus includes an input buffer comprising an amplifier coupled to a pair of serially coupled inverters, and a de-emphasis circuit coupled to the input buffer in parallel with one of the pair of serially-coupled inverters. The de-emphasis circuit comprising a plurality of transistors coupled in parallel to a resistance. The example apparatus further includes an input buffer control circuit configured to selectively enable one of the plurality of transistors to adjust a gain across the one of the pair of inverters based on a latency setting.Type: ApplicationFiled: December 17, 2020Publication date: June 23, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Akira Yamashita, Kenji Asaki
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Publication number: 20220011809Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.Type: ApplicationFiled: September 27, 2021Publication date: January 13, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Kenji Asaki, Shuichi Tsukada
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Patent number: 11132015Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.Type: GrantFiled: February 8, 2019Date of Patent: September 28, 2021Assignee: Micron Technology, Inc.Inventors: Kenji Asaki, Shuichi Tsukada
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Patent number: 10985753Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. As example apparatus includes a power supply line configured to provide a supply voltage and further includes first and second nodes. An impedance element is coupled between the power supply line and the first node and a first transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. A reference line is configured to provide a reference voltage. A second transistor has a gate, a source coupled to the reference line, and a drain. The gate and the drain of the second transistor are coupled to the gate of the first transistor.Type: GrantFiled: December 21, 2018Date of Patent: April 20, 2021Assignee: Micron Technology, Inc.Inventors: Kenji Asaki, Shuichi Tsukada
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Publication number: 20200257331Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.Type: ApplicationFiled: February 8, 2019Publication date: August 13, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Kenji Asaki, Shuichi Tsukada
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Patent number: 10559343Abstract: A memory device includes an internal storage unit configured to store mode data specifying an operating speed of the memory device; a control decoder coupled to the internal storage unit, the control decoder configured to generate a delay control signal based on the mode data; and an input buffer coupled to the control decoder, the input buffer configured to adjust a delay of an input signal based on the delay control signal.Type: GrantFiled: July 10, 2019Date of Patent: February 11, 2020Assignee: Micron Technology, Inc.Inventors: Akira Yamashita, Kenji Asaki
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Publication number: 20200027494Abstract: A memory device includes an internal storage unit configured to store mode data specifying an operating speed of the memory device; a control decoder coupled to the internal storage unit, the control decoder configured to generate a delay control signal based on the mode data; and an input buffer coupled to the control decoder, the input buffer configured to adjust a delay of an input signal based on the delay control signal.Type: ApplicationFiled: July 10, 2019Publication date: January 23, 2020Inventors: Akira Yamashita, Kenji Asaki
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Patent number: 10438650Abstract: A memory device includes an internal storage unit configured to store mode data specifying an operating speed of the memory device; a control decoder coupled to the internal storage unit, the control decoder configured to generate a delay control signal based on the mode data; and an input buffer coupled to the control decoder, the input buffer configured to adjust a delay of an input signal based on the delay control signal.Type: GrantFiled: July 20, 2018Date of Patent: October 8, 2019Assignee: Micron Technology, Inc.Inventors: Akira Yamashita, Kenji Asaki
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Patent number: 10373655Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. An example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value. The bias circuit continues to decrease the bias current as the supply voltage further increases from the second value in a first operation mode. The bias circuit also prevents the bias current from decreasing against a further increase of the supply voltage from the second value in a second operation mode.Type: GrantFiled: December 6, 2017Date of Patent: August 6, 2019Assignee: Micron Technology, Inc.Inventors: Kenji Asaki, Shuichi Tsukada, Sachiko Edo
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Publication number: 20190172507Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. As example apparatus includes a power supply line configured to provide a supply voltage and further includes first and second nodes. An impedance element is coupled between the power supply line and the first node and a first transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. A reference line is configured to provide a reference voltage. A second transistor has a gate, a source coupled to the reference line, and a drain. The gate and the drain of the second transistor are coupled to the gate of the first transistor.Type: ApplicationFiled: December 21, 2018Publication date: June 6, 2019Inventors: Kenji Asaki, Shuichi Tsukada
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Publication number: 20190172505Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. An example apparatus includes a power supply configured to provide a supply voltage and further includes a bias circuit coupled to the power supply to produce a bias current. The bias circuit is configured to decrease the bias current as the supply voltage increases from a first value to a second value. The bias circuit continues to decrease the bias current as the supply voltage further increases from the second value in a first operation mode. The bias circuit also prevents the bias current from decreasing against a further increase of the supply voltage from the second value in a second operation mode.Type: ApplicationFiled: December 6, 2017Publication date: June 6, 2019Applicant: MICRON TECHNOLOGY, INC.Inventors: Kenji Asaki, Shuichi Tsukada, Sachiko Edo
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Patent number: 10199081Abstract: Apparatuses and methods for providing bias signals in a semiconductor device are described. As example apparatus includes a power supply line configured to provide a supply voltage and further includes first and second nodes. An impedance element is coupled between the power supply line and the first node and a first transistor having a gate, a source coupled to the first node, and a drain coupled to the second node. A reference line is configured to provide a reference voltage. A second transistor has a gate, a source coupled to the reference line, and a drain. The gate and the drain of the second transistor are coupled to the gate of the first transistor.Type: GrantFiled: December 6, 2017Date of Patent: February 5, 2019Assignee: Micron Technology, Inc.Inventors: Kenji Asaki, Shuichi Tsukada
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Patent number: 9484075Abstract: A semiconductor device includes data terminal, unit buffers which drive the data terminal and the impedance of which can be adjusted, and control circuits which successively switch the operation of at least two unit buffers selected from unit buffers. Because the operation of the plurality of unit buffers is switched successively, the peak current which flows during an output operation is dispersed, power-supply noise can be controlled, and the output potential can be switched very rapidly and continuously, while a fixed output impedance is maintained.Type: GrantFiled: September 11, 2013Date of Patent: November 1, 2016Assignee: PS4 LUXCO S.A.R.L.Inventors: Tetsuya Arai, Kenji Asaki
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Publication number: 20150235679Abstract: A semiconductor device includes data terminal, unit buffers which drive the data terminal and the impedance of which can be adjusted, and control circuits which successively switch the operation of at least two unit buffers selected from unit buffers. Because the operation of the plurality of unit buffers is switched successively, the peak current which flows during an output operation is dispersed, power-supply noise can be controlled, and the output potential can be switched very rapidly and continuously, while a fixed output impedance is maintained.Type: ApplicationFiled: September 11, 2013Publication date: August 20, 2015Applicant: PS4 LUXCO S.A.R.L.Inventors: Tetsuya Arai, Kenji Asaki