Patents by Inventor Kenji Hanada

Kenji Hanada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8557633
    Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: October 15, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Kunio Shigemura, Kenji Hanada, Masaki Nakanishi, Takafumi Nishita, Masayoshi Shinoda, Seiichi Tomoi
  • Publication number: 20110183474
    Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.
    Type: Application
    Filed: April 5, 2011
    Publication date: July 28, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Kunio Shigemura, Kenji Hanada, Masaki Nakanishi, Takafumi Nishita, Masayoshi Shinoda, Seiichi Tomoi
  • Publication number: 20080253100
    Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.
    Type: Application
    Filed: June 12, 2008
    Publication date: October 16, 2008
    Inventors: Kunio Shigemura, Kenji Hanada, Masaki Nakanishi, Takafumi Nishita, Masayoshi Shinoda, Seiichi Tomoi
  • Publication number: 20080248611
    Abstract: The quality and reliability of a semiconductor device can be improved by eliminating a warp of a chip and performing a chip-stack. A wiring substrate, the first semiconductor chip connected via the first gold bump on the wiring substrate, the second semiconductor chip stacked via the second gold bump on the first semiconductor chip, and a sealing body are comprised. A first gold bump is connected to the wiring substrate, heating, and injection by pressure welding of the first gold bump is done under normal temperature after that at the hole-like electrode of the first semiconductor chip. Since injection by pressure welding of the second gold bump of the second semiconductor chip is done under normal temperature into the hole-like electrode of the first semiconductor chip and the second semiconductor chip is stacked, the chip-stack can be performed under normal temperature.
    Type: Application
    Filed: February 27, 2008
    Publication date: October 9, 2008
    Inventors: Kenji HANADA, Norihisa Toma, Masaki Nakanishi, Takahiro Naito, Naotaka Tanaka
  • Patent number: 7396701
    Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kunio Shigemura, Kenji Hanada, Masaki Nakanishi, Takafumi Nishita, Masayoshi Shinoda, Seiichi Tomoi
  • Patent number: 7168161
    Abstract: In a method of manufacturing a camera module having a CMOS image sensor, a semiconductor chip to serve as a light sensor is mounted on a optical-component-mounting face of a wiring substrate mother board and, after bonding wires are connected to the semiconductor chip, a lens barrel is joined to the wiring substrate mother board so as to cover the semiconductor chip. A position adjustment pin and a through hole are provided on the lens barrel and the wiring substrate mother board respectively outside a junction face between the lens barrel and the wiring substrate mother board to be used for adjusting the position of the lens barrel with respect to the wiring substrate mother board by inserting the position adjustment pin into the through hole.
    Type: Grant
    Filed: September 11, 2003
    Date of Patent: January 30, 2007
    Assignees: Renesas Technology Corp., Renesas Eastern Japan Semiconductor Inc.
    Inventors: Kenji Hanada, Akio Ishizu
  • Publication number: 20060248715
    Abstract: In a method of manufacturing a camera module having a CMOS image sensor, a semiconductor chip to serve as a light sensor is mounted on a optical-component-mounting face of a wiring substrate mother board and, after bonding wires are connected to the semiconductor chip, a lens barrel is joined to the wiring substrate mother board so as to cover the semiconductor chip. A position adjustment pin and a through hole are provided on the lens barrel and the wiring substrate mother board respectively outside a junction face between the lens barrel and the wiring substrate mother board to be used for adjusting the position of the lens barrel with respect to the wiring substrate mother board by inserting the position adjustment pin into the through hole.
    Type: Application
    Filed: July 5, 2006
    Publication date: November 9, 2006
    Inventors: Kenji Hanada, Akio Ishizu
  • Publication number: 20060110859
    Abstract: A technique that makes it possible to enhance the reliability of a module using PCB as its module substrate is provided. Solder connection of a single-chip component 43, an integrated chip component 44, and a semiconductor chip IC2 by Pb-free solder is carried out by heat treatment at a temperature below 280° C. using a heat block. Solder connection of a semiconductor chip IC1 by high-melting point solder is carried out by heat treatment at a temperature of 280° C. or higher using a hot jet. Thus, the semiconductor chip IC1 can be solder connected to PCB 38 using high-melting point solder without the following troubles: damage to the PCB 38 due to heat, for example, burning of solder resist; and peeling of prepreg from a core material. Therefore, the semiconductor chip IC1 can be mounted over the PCB 38 with high connection strength.
    Type: Application
    Filed: November 18, 2005
    Publication date: May 25, 2006
    Inventors: Kunio Shigemura, Kenji Hanada, Masaki Nakanishi, Takafumi Nishita, Masayoshi Shinoda, Seiichi Tomoi
  • Publication number: 20060091487
    Abstract: A sensor chip and a lens mount accommodating therein the sensor chip are mounted on a surface of a wiring substrate and a lens holder accommodating a lens therein is coupled with the lens mount. On a rear surface of the wiring substrate, a logic chip, a memory chip and a passive component are mounted and they are sealed with a seal resin. An electrode pad of the sensor chip is electrically connected to an electrode on the surface of the wiring substrate via a bonding wire but a stud bump is also formed on the electrode at the surface of the wiring substrate and this stud bump is connected with the bonding wire. On the surface of the wiring substrate, a flexible substrate is bonded with an anisotropic conductive film and a bonding material. When a camera module is to be manufactured, the surface side of the wiring substrate is assembled after the rear surface side of the wiring substrate is assembled.
    Type: Application
    Filed: December 16, 2005
    Publication date: May 4, 2006
    Inventors: Kenji Hanada, Masaki Nakanishi, Tomoo Matsuzawa, Koji Shida, Kazutoshi Takashima
  • Patent number: 7005310
    Abstract: A sensor chip and a lens mount accommodating therein the sensor chip are mounted on a surface of a wiring substrate and a lens holder accommodating a lens therein is coupled with the lens mount. On a rear surface of the wiring substrate, a logic chip, a memory chip and a passive component are mounted and they are sealed with a seal resin. An electrode pad of the sensor chip is electrically connected to an electrode on the surface of the wiring substrate via a bonding wire but a stud bump is also formed on the electrode at the surface of the wiring substrate and this stud bump is connected with the bonding wire. On the surface of the wiring substrate, a flexible substrate is bonded with an anisotropic conductive film and a bonding material. When a camera module is to be manufactured, the surface side of the wiring substrate is assembled after the rear surface side of the wiring substrate is assembled.
    Type: Grant
    Filed: August 29, 2003
    Date of Patent: February 28, 2006
    Assignees: Renesas Technology Corporation, Renesas Eastern Japan Semiconductor, Inc.
    Inventors: Kenji Hanada, Masaki Nakanishi, Tomoo Matsuzawa, Koji Shida, Kazutoshi Takashima
  • Publication number: 20050116138
    Abstract: The reliability and production yield of a solid state image sensing device is improved. Over a surface of a wiring substrate, a sensor chip and a lens-barrel having the sensor chip housed therein are mounted. To the lens-barrel, a lens holder for retaining a lens is connected. Over a back surface of the wiring substrate, a logic chip, a memory chip and a passive part are mounted, and they are sealed with a sealing resin. The lens-barrel and lens holder are each threaded. They are thermally welded while the threads are fitted to each other. The passive part is bonded to the wiring substrate via a Sn—Ag type Pb-free solder. After the wiring substrate is subjected to plasma washing treatment, the sensor chip is mounted over the wiring substrate and an electrode pad of the sensor chip and an electrode of the wiring substrate are electrically connected via a bonding wire.
    Type: Application
    Filed: September 22, 2004
    Publication date: June 2, 2005
    Inventors: Kenji Hanada, Masaki Nakanishi, Kunio Shigemura, Takaomi Nishi, Koji Shida, Izumi Tezuka, Shunichi Abe, Yoshihiro Tomita, Mitsuaki Seino, Tohru Komatsu
  • Publication number: 20050048692
    Abstract: In a method of manufacturing a camera module having a CMOS image sensor, a semiconductor chip to serve as a light sensor is mounted on a optical-component-mounting face of a wiring substrate mother board and, after bonding wires are connected to the semiconductor chip, a lens barrel is joined to the wiring substrate mother board so as to cover the semiconductor chip. A position adjustment pin and a through hole are provided on the lens barrel and the wiring substrate mother board respectively outside a junction face between the lens barrel and the wiring substrate mother board to be used for adjusting the position of the lens barrel with respect to the wiring substrate mother board by inserting the position adjustment pin into the through hole.
    Type: Application
    Filed: September 11, 2003
    Publication date: March 3, 2005
    Inventors: Kenji Hanada, Akio Ishizu
  • Publication number: 20040166763
    Abstract: A sensor chip and a lens mount accommodating therein the sensor chip are mounted on a surface of a wiring substrate and a lens holder accommodating a lens therein is coupled with the lens mount. On a rear surface of the wiring substrate, a logic chip, a memory chip and a passive component are mounted and they are sealed with a seal resin. An electrode pad of the sensor chip is electrically connected to an electrode on the surface of the wiring substrate via a bonding wire but a stud bump is also formed on the electrode at the surface of the wiring substrate and this stud bump is connected with the bonding wire. On the surface of the wiring substrate, a flexible substrate is bonded with an anisotropic conductive film and a bonding material. When a camera module is to be manufactured, the surface side of the wiring substrate is assembled after the rear surface side of the wiring substrate is assembled.
    Type: Application
    Filed: August 29, 2003
    Publication date: August 26, 2004
    Inventors: Kenji Hanada, Masaki Nakanishi, Tomoo Matsuzawa, Koji Shida, Kazutoshi Takashima
  • Patent number: 6400019
    Abstract: The junction strength between the external terminals and the wiring substrate of a semiconductor device is improved without creating a large size semiconductor device. In the outer periphery of the back surface of an interposer substrate 1Bi on which a semiconductor chip constructing a CSP type semiconductor device 1 is mounted, there are arranged a plurality of bump electrodes 1BB1 whose size in the direction intersecting the sides of the interposer substrate 1B1 is larger than that in the direction along the sides of the interposer substrate 1Bi.
    Type: Grant
    Filed: November 9, 2000
    Date of Patent: June 4, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Toshinori Hirashima, Yasushi Takahashi, Kenji Hanada, Takao Sonobe
  • Patent number: 6335566
    Abstract: Disclosed herein is a semiconductor device in which a main surface of a semiconductor chip is placed over a first main surface of a wiring board so as to be opposed thereto and which includes a plurality of external terminals provided over a second main surface of the wiring board. The plurality of external terminals have a plurality of signal terminals and a plurality of power terminals. The signal terminals are arranged along the periphery of the wiring board and the power terminals are arranged along the inside of a row of the signal terminals. Chip capacitors are placed over the main surface of the semiconductor chip, which lies inside a row of the power terminals. The plurality of signal terminals and power terminals formed over the main surface of the semiconductor chip are connected to a plurality of wires formed over the wiring board respectively. The wiring board is provided with an opening or recess which extends therethrough. The chip capacitors are located within the opening or recess.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: January 1, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd., Hitachi Tohbu Semiconductor, Ltd.
    Inventors: Toshinori Hirashima, Takefumi Endo, Kazuo Watanabe, Kenji Hanada, Takao Sonobe