Patents by Inventor Kenji Hiruma
Kenji Hiruma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130244146Abstract: After performing a pretreatment step of coating an organic solvent mixed with a polymeric organic compound over a substrate having a tungsten film formed on the surface of the substrate, a chemically amplified resist is coated to form a resist pattern. Further, a ratio of a C1s peak intensity to a W4d peak intensity measured by XPS is 0.1 or mote at the surface of the tungsten film after the pretreatment step and before coating the chemically amplified resist.Type: ApplicationFiled: February 4, 2013Publication date: September 19, 2013Applicant: HITACHI, LTD.Inventors: Kazuyuki Kakuta, Toshio Ando, Kenji Hiruma, Toshihiko Onozuka, Kiyomi Katsuyama, Kiyohiko Satoh, Yasushi IIDA
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Patent number: 8519378Abstract: Semiconductor surface emitting elements having a plurality of wavelengths being manufactured on a signal substrate through MOVPE selective growth. More specifically, provided is a semiconductor light emitting element array which comprises; a semiconductor crystal substrate; an insulating film disposed on a surface of the substrate, the insulating film being divided into two or more regions, each of which having two or more openings exposing the surface of the substrate; semiconductor rods extending from the surface of the substrate upward through the openings, the semiconductor rods each having an n-type semiconductor layer and a p-type semiconductor layer being laminated in its extending direction, thereby providing a p-n junction; a first electrode connected to the semiconductor crystal substrate; and a second electrode connected to upper portions of the semiconductor rods; wherein the heights of the semiconductor rods as measured from the substrate surface vary by each of the two or more regions.Type: GrantFiled: October 17, 2008Date of Patent: August 27, 2013Assignees: National University Corporation Hokkaido University, Sharp Kabushiki KaishaInventors: Kenji Hiruma, Shinjiro Hara, Junichi Motohisa, Takashi Fukui
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Publication number: 20110204327Abstract: Semiconductor surface emitting elements having a plurality of wavelengths being manufactured on a signal substrate through MOVPE selective growth. More specifically, provided is a semiconductor light emitting element array which comprises; a semiconductor crystal substrate; an insulating film disposed on a surface of the substrate, the insulating film being divided into two or more regions, each of which having two or more openings exposing the surface of the substrate; semiconductor rods extending from the surface of the substrate upward through the openings, the semiconductor rods each having an n-type semiconductor layer and a p-type semiconductor layer being laminated in its extending direction, thereby providing a p-n junction; a first electrode connected to the semiconductor crystal substrate; and a second electrode connected to upper portions of the semiconductor rods; wherein the heights of the semiconductor rods as measured from the substrate surface vary by each of the two or more regions.Type: ApplicationFiled: October 17, 2008Publication date: August 25, 2011Applicant: NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITYInventors: Kenji Hiruma, Shinjiro Hara, Junichi Motohisa, Takashi Fukui
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Publication number: 20110155236Abstract: To provide a solar cell enabling practical electric power to be obtained and excitons to be effectively collected, and a manufacturing method of the solar cell. A nanowire solar cell 1 comprises: a semiconductor substrate 2; a plurality of nanowire semiconductors 4 and 5 forming pn junctions; a transparent insulating material 6 filled in the gap between the plurality of nanowire semiconductors 4 and 5; an electrode 7 covering the end portion of the plurality of nanowire semiconductors 4 and 5; and a passivation layer 10 provided between the semiconductor 5 and the transparent insulating material 6 and between the semiconductor 5 and the electrode 7.Type: ApplicationFiled: December 22, 2010Publication date: June 30, 2011Inventors: Hajime Goto, Takashi Fukui, Junichi Motohisa, Kenji Hiruma
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Publication number: 20110126891Abstract: A solar cell element having improved power generation efficiency is provided. A solar cell element 100 has a substrate 110, a mask pattern 120, semiconductor nanorods 130, a first electrode 150 and a second electrode 160. The semiconductor nanorods 130 are disposed in triangular lattice form as viewed in plan on the substrate 110. The ratio p/d of the center-to-center distance p between each adjacent pair of the semiconductor nanorods 130 and the minimum diameter d of the semiconductor nanorods 130 is within the range from 1 to 7. Each semiconductor nanorod 130 has a central nanorod 131 formed of a semiconductor of a first conduction type, a first cover layer 132 formed of an intrinsic semiconductor and covering the central nanorod 131, and a second cover layer 138 formed of a semiconductor of a second conduction type and covering the first cover layer 132.Type: ApplicationFiled: November 29, 2010Publication date: June 2, 2011Inventors: Hajime Goto, Hirotaka Endo, Kenji Hiruma, Junichi Motohisa, Takashi Fukui
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Patent number: 6356572Abstract: It is an object of the present invention to provide a semiconductor light emitting device capable of securing, in use of an optical information processing or an optical communication system, a low threshold and high efficiency operation as well as a high output characteristic. An active layer structure having a flatness and an interface acuteness of a quantum well structure improved by introducing a multi-period super lattice structure between a substrate for crystal growth and a light emitting layer area further to on a misoriented substrate sued to enhance a homogeneity of a semiconductor crystal. Further, a carrier confinement and a light confinement can be enhanced by providing a margin for design of the quantum well structure.Type: GrantFiled: March 16, 1999Date of Patent: March 12, 2002Assignee: Hitachi, Ltd.Inventors: Toshiaki Tanaka, Kenji Hiruma, Hiroshi Hamada
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Patent number: 5701019Abstract: A semiconductor device (e.g., hetero-junction field-effect transistor) which has decreased capacitance between the gate and drain, and which has decreased source resistance, is provided. Structure in which a contact layer 6 comes in contact with the side surfaces of a channel layer 3 but does not come in contact with the side surfaces of a barrier layer 4 enables capacitance between the gate and drain to be decreased. This capacitance can be decreased down to 1.5 pF per 10 .mu.m of the width.Type: GrantFiled: August 21, 1995Date of Patent: December 23, 1997Assignee: Hitachi, Ltd.Inventors: Hidetoshi Matsumoto, Masamitsu Yazawa, Kenji Hiruma
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Patent number: 5381027Abstract: This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by intoduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance.Type: GrantFiled: October 12, 1993Date of Patent: January 10, 1995Assignee: Hitachi, Ltd.Inventors: Toshiyuki Usagawa, Kenji Hiruma, Masahiko Kawata, Shigeo Goto, Katsuhiko Mitani, Masao Yamane, Susumu Takahashi, Tomonori Tanoue, Yoshinori Imamura
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Patent number: 5362972Abstract: A field effect transistor and a ballistic transistor using semiconductor whiskers each having a desired diameter and formed at s desired location, a semiconductor vacuum microelectronic device using the same as electron emitting materials, a light emitting device using the same as quantum wires and the like are disclosed.Type: GrantFiled: April 17, 1991Date of Patent: November 8, 1994Assignees: Hitachi, Ltd., Hitachi VLSI Engineering CorporationInventors: Masamitsu Yazawa, Kenji Hiruma, Toshio Katsuyama, Nobutaka Futigami, Hidetoshi Matsumoto, Hiroshi Kakibayashi, Masanari Koguchi, Gerard P. Morgan, Kensuke Ogawa
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Patent number: 5351128Abstract: A field-effect transistor or a bipolar transistor may be provided in which the contact resistance between a channel layer or base layer and a contact layer are reduced. For example, an InGaAs buffer layer may be formed on the substrate side of an InGaAs channel layer of a field-effect transistor and by the bypassing effect that carriers pass through this InGaAs buffer layer, the InGaAs channel layer comes in contact with the contact layer with a low resistance. The contact resistance between the InGaAs channel layer and the contact layer can be reduced to 10 ohm per a width of 10.mu.m, and as a result, the value of transconductance factor K of a field-effect transistor can be increased in 14 mA/V.sup.2 per a width of 10.mu.m.Type: GrantFiled: July 27, 1992Date of Patent: September 27, 1994Assignee: Hitachi, Ltd.Inventors: Shigeo Goto, Hidetoshi Matsumoto, Masamitsu Yazawa, Yasunari Umemoto, Yoko Uchida, Kenji Hiruma
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Patent number: 5332910Abstract: A semiconductor light-emitting device includes a plurality of semiconductor rods, each of which has a pn junction. The semiconductor rods are formed on a semiconductor substrate such that the plurality of semiconductor rods are arranged at a distance substantially equal to an integer multiple of the wavelength of light emitted from the semiconductor rod. With such devices, various novel optical devices such as a micro-cavity laser of which the threshold current is extremely small and a coherent light-emitting device having no threshold value can be realized.Type: GrantFiled: November 30, 1993Date of Patent: July 26, 1994Assignee: Hitachi, Ltd.Inventors: Keiichi Haraguchi, Kenji Hiruma, Kensuke Ogawa, Toshio Katsuyama, Ken Yamaguchi, Toshiyuki Usagawa, Masamits Yazawa, Toshiaki Masuhara, Gerard P. Morgan, Hiroshi Kakibayashi
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Patent number: 5258631Abstract: This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by introduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance.Type: GrantFiled: May 18, 1992Date of Patent: November 2, 1993Assignee: Hitachi, Ltd.Inventors: Toshiyuki Usagawa, Kenji Hiruma, Masahiko Kawata, Shigeo Goto, Katsuhiko Mitani, Masao Yamane, Susumu Takahashi, Tomonori Tanoue, Yoshinori Imamura
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Patent number: 5025751Abstract: A solid film forming apparatus, e.g., an MO-MBE (Metal-Organic Molecular Beam Epitaxy) apparatus, wherein evacuatable containers isolated from a growth chamber by a switching device and connected to raw material gas introduction pipings are provided between the growth chamber for a solid film, e.g., a compound semiconductor, and raw material gas introduction pipings. Growth of the solid film is controlled by opening and closing the switching device and evacuating the container at least while the switching device is closed during the growth of the solid film. An undesired influence on the growing film due to residual gas in the containers which are not used for growth can be prevented and, hence, interception and introduction of the raw material gas into the growth chamber can be performed with remarkably high controllability, and films of superior abruptness of the interface between films, e.g., the heterojunction of the compound semiconductor, can be obtained.Type: GrantFiled: June 14, 1989Date of Patent: June 25, 1991Assignee: Hitachi, Ltd.Inventors: Shinichiro Takatani, Shigeo Goto, Masahiko Kawata, Kenji Hiruma
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Patent number: 4933728Abstract: A semiconductor optical device in which a hetero-structure is constructed by sandwiching a semiconductor layer including a thin film made of a semiconductor or insulator between semiconductors having a larger band gap than that of the thin film so that the electron-hole pairs generated through the thin film may recombine by the tunnel effect to emit an optical beam. The optical device is equipped with electrodes for controlling the probability of said recombination.Type: GrantFiled: February 13, 1989Date of Patent: June 12, 1990Assignee: Hitachi, Ltd.Inventors: Tadashi Fukuzawa, Eizaburo Yamada, Kenji Hiruma, Hiroyoshi Matsumura
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Patent number: 4847573Abstract: An optical modulator which utilizes the Stark effect according to which the absorption spectra change if an electric field is applied to the excitons. A thin film of a suitable thickness composed of a semiconductor and an insulator or composed of either one of them, is formed between a group of electrons and a group of positive holes that constitute excitons, so that the excitons are stabilized. The optical modulator performs the modulation at high speeds maintaining a high efficiency.Type: GrantFiled: May 7, 1986Date of Patent: July 11, 1989Assignee: Hitachi, Ltd.Inventors: Tadashi Fukuzawa, Eizaburo Yamada, Kenji Hiruma, Hiroyoshi Matsumura
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Patent number: 4835583Abstract: An epitaxial crystal grown layer structure which permits, on an In-doped GaAs substrate, which will be industrially used in large quantities, the growth of an epitaxial layer having the same good quality as the epitaxial layer grown on an undoped GaAs substrate.Type: GrantFiled: August 13, 1986Date of Patent: May 30, 1989Assignee: Hitachi, Ltd.Inventors: Makoto Morioka, Tomoyoshi Mishima, Kenji Hiruma, Yoshifumi Katayama, Yasuhiro Shiraki
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Patent number: 4784451Abstract: The present invention provides a waveguide type optical switch which has a high extinction ratio and can be driven efficiently at a low voltage or a low current injection. Where the waveguide type optical switch is used as a reflection type optical switch, the switch section is of current confinement structure, and where it is used as a directional coupler type optical switch, the pn junction is formed in the position where the optical electric field takes the maximum value for the fundamental mode of the light propagating in the waveguide.Type: GrantFiled: August 5, 1985Date of Patent: November 15, 1988Assignee: Hitachi, Ltd.Inventors: Hitoshi Nakamura, Tadashi Fukuzawa, Koji Ishida, Hiroyoshi Matumura, Kenji Hiruma, Hiroaki Inoue
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Patent number: 4775980Abstract: A distributed feedback semiconductor laser provided with a grating which effects optical feedback by means of periodic corrugation disposed inside an optical resonator. The optical resonator has at least two regions having different Bragg wavelengths, and these regions are arranged longitudinally in the direction of an optical axis. The laser device can realize stable single longitudinal mode oscillation through variation of the refractive indexes of the regions nonuniformly around an average value.Type: GrantFiled: July 26, 1985Date of Patent: October 4, 1988Assignee: Hitachi, Ltd.Inventors: Naoki Chinone, Shinji Tsuji, Yoshihisa Fujisaki, Yasutoshi Kashiwada, Motohisa Hirao, Hitoshi Nakamura, Akio Oishi, Kenji Hiruma, Tadashi Fukuzawa, Hiroyoshi Matumura
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Patent number: 4766092Abstract: When a semiconductor device is produced by growing epitaxially a compound semiconductor layer on a Si or Ge substrate, lattice matching between the substrate crystal and the compound semiconductor layer to be formed on the substrate can be improved by ion-implanting an ion species element, which increases the lattice constant of Si or Ge as the substrate, into the Si or Ge substrate in order to increase its lattice constant. In comparison with conventional semiconductor devices using Si or Ge into which ion implantation is not made, the semiconductor device produced by the method described above can improve remarkably its characteristics. In the case of a semiconductor laser device, for example, its threshold value drops drastically and its service life can be prolonged remarkably.Type: GrantFiled: December 2, 1986Date of Patent: August 23, 1988Assignee: Hitachi, Ltd.Inventors: Takao Kuroda, Kenji Hiruma, Hiroyoshi Matsumura
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Patent number: 4737015Abstract: An optical waveguide comprising a layer formed on a substrate, having a mixed composition of silicon oxide and silicon nitride and having an arbitrary value of refractive index ranging between those of the silicon oxide and the silicon nitride. The layer of said mixed composition can be formed on the substrate to easily fabricate the optical waveguide of the present invention by conducting a sputtering method employing a Si target and controlling the composition of a sputtering gas composed of a mixture of N.sub.2 and O.sub.2 gases.Type: GrantFiled: November 26, 1984Date of Patent: April 12, 1988Assignee: Hitachi, Ltd. Hitachi CabelInventors: Koji Ishida, Hiroyoshi Matsumura, Kenji Hiruma, Kazuyuki Nagatsuma, Akihito Hongo