Abstract: A lift amount variable mechanism is configured to switch a cam for driving an intake valve (drive cam) between two types of intake cams in lift amount (i.e. a large lift cam and a small lift cam). In a first embodiment of this disclosure, the lift amount variable mechanism is controlled by an ECU so that the small lift cam is selected as the drive cam for control that promotes activation of an exhaust gas cleaning catalyst (catalyst warm-up control).

Abstract: An intake stroke injection and a compression stroke injection are performed during catalyst warm-up control (upper section in FIG. 7). During the catalyst warm-up control, a discharge period at an electrode portion is set on a retard side of compression top dead center, and an expansion stroke injection is performed during the discharge period. However, when a distance between a spray contour surface and the electrode portion increases, an additional injection (first injection) is performed in advance of the expansion stroke injection (second injection) (lower section in FIG. 7). The additional injection is performed at a timing that is on the retard side of compression top dead center and is on an advance side relative to a start timing of the discharge at the electrode portion.

Abstract: A control apparatus for an internal combustion engine, wherein the internal combustion engine includes a fuel injection valve injecting fuel directly into a cylinder. The control apparatus includes an ECU. The ECU is configured to execute a divided injection control to inject fuel from the fuel injection valve by a plurality of partial lift injections. The ECU is configured to execute a division number reduction control when the value of a spray shape parameter representing spray shape fluctuation is greater than a division number reduction determination value. The division number reduction control is control to reduce the number of partial lift injections in one engine cycle and to lengthen an injection time of each of the partial lift injections.

Abstract: In an in-cylinder injection spark-ignition internal combustion engine, in which fuel is injected toward a cavity formed in a crown surface of a piston, when split injection for dividing and injecting the fuel for plural times is performed during a compression stroke, an arrival lift amount that is a maximum value of displacement of a valve body of a fuel injection valve during fuel injection is set as a larger value at least in a first period as a crank angle of the internal combustion engine approaches compression top dead center.

Abstract: A control apparatus for an internal combustion engine, wherein the internal combustion engine includes a fuel injection valve injecting fuel directly into a cylinder. The control apparatus includes an ECU. The ECU is configured to execute a divided injection control to inject fuel from the fuel injection valve by a plurality of partial lift injections. The ECU is configured to execute a division number reduction control when the value of a spray shape parameter representing spray shape fluctuation is greater than a division number reduction determination value. The division number reduction control is control to reduce the number of partial lift injections in one engine cycle and to lengthen an injection time of each of the partial lift injections.

Abstract: Strip-shaped alignment marks 14 are juxtaposed with each other in a silicon oxide film 12 formed on a silicon wafer 10. Each alignment mark 14 comprises a plurality of grooves 16 formed side by side in the silicon oxide film 12. An amorphous silicon film 18 is buried in the grooves 16. Thus, the alignment marks 14 are formed in a thus-formed line-and-space pattern. Accordingly, waveforms of detected signals having high contrast and little deformation can be obtained, and alignment of wafers with high accuracy can be realized.

Abstract: Strip-shaped alignment marks 14 are juxtaposed with each other in a silicon oxide film 12 formed on a silicon wafer 10. Each alignment mark 14 comprises a plurality of grooves 16 formed side by side in the silicon oxide film 12. An amorphous silicon film 18 is buried in the grooves 16. Thus, the alignment marks 14 are formed in a thus-formed line-and-space pattern. Accordingly, waveforms of detected signals having high contrast and little deformation can be obtained, and alignment of wafers with high accuracy can be realized.

Abstract: There is provided an information processing device having information processing units between which data can be transferred via a bus provided therebetween. A data requested unit which is one of the information processing units sends an answering signal to a data requesting unit which is another one thereof. The information processing device includes an error detecting part for detecting an error in received data, an answering signal generating part for generating an error answering signal with respect to received data having an error and a normality answering signal with respect to received data having no error, and an information sending part for sending the error answering signal to the bus with priority over the normality answering signal.

Abstract: In an access processing system in an information processor, the information processor includes: an access device (10, 11) for generating an access request signal; an accessed device (13) provided with a memory means (30) that is accessed by the access device (10, 11); and an address bus (14) that has the access device and accessed device connected with the information processor at least by the address bus (14).The access processing system is processed such that, if an access request is produced, when the access request signal does not require all bits in the address bus (14), an unused bit in the address bus (14) is loaded with write data to deliver it to the accessed device (13).

Abstract: In a clock control circuit for suppressing a clock pulse in a plurality of devices which operate in synchronization with each other, the clock control circuit detects first and second clock suppress conditions, generates a first clock suppress signal in all the devices based on the detection of the first clock suppress condition, generates a second clock suppress signal in a particular device based on the detection of the first or second clock suppress conditions, transmits the clock suppress signals to all the devices, and suppresses the clock pulse in all the devices based on the first and second clock suppress signals. The second clock suppress signal suppresses the clock pulse after it is suppressed by the first clock suppress signal, and continues to suppress the clock pulse until a suppression release signal is received.