Abstract: Systems and methods for bypassing lower level caches and enabling direct access to higher level caches in order to provide fixed data latency and increased amounts of immediately accessible storage. One embodiment comprises a memory system having multiple cache memories that have increasing data latencies and amounts of storage. In a first mode which is suitable to support a microprocessor mode of a dual-mode processor, each data access proceeds conventionally, with accesses to successively higher levels of cache memory. In a second mode which is suitable to support a DSP mode of the dual-mode processor, the memory system bypasses the lower level cache and directly accesses the higher level cache in order to achieve a fixed latency (with enough cache storage to be useful to operate the processor in a DSP mode.

Abstract: Systems and methods for performing design verification testing in which test cases are analyzed to determine the characteristics that will be verified in a module under test, and in which the identified characteristics are used to selectively enable checker modules needed to verify the characteristics implicated by the test cases, while disabling other checker modules. In one embodiment, a system includes a test case analyzer and a checker selector. The test case analyzer analyzes one or more test cases and identifies test case characteristics that are associated with each of the test cases. The checker selector is coupled to the test case analyzer and receives identification of the test case characteristics from the test case analyzer. The checker selector then selectively enables a first set of design verification checkers and disables a second set, based on the test case characteristics identified for the test cases.

Abstract: Systems and methods for bypassing lower level caches and enabling direct access to higher level caches in order to provide fixed data latency and increased amounts of immediately accessible storage. One embodiment comprises a memory system having multiple cache memories that have increasing data latencies and amounts of storage. In a first mode which is suitable to support a microprocessor mode of a dual-mode processor, each data access proceeds conventionally, with accesses to successively higher levels of cache memory. In a second mode which is suitable to support a DSP mode of the dual-mode processor, the memory system bypasses the lower level cache and directly accesses the higher level cache in order to achieve a fixed latency (with enough cache storage to be useful to operate the processor in a DSP mode.

Abstract: Systems and methods for determining dependencies between processor instructions in multiple phases. In one embodiment, a partial comparison is made between the addresses of a sequence of instructions. Younger instructions having potential dependencies on older instructions are suspended if the partial comparison yields a match. One or more subsequent comparisons are made for suspended instructions based on portions of the addresses referenced by the instructions that were not previously compared. If subsequent comparisons determine that the addresses of the instructions do not match, the suspended instructions are reinstated and execution of the suspended instructions is resumed. In one embodiment, data needed by suspended instructions is speculatively requested in case the instructions are reinstated.

Abstract: Systems and methods for modes of operation for processing data are disclosed. While executing a program in one mode the hazard checking logic present in the microprocessor system may be utilized to check or ameliorate the hazards caused by the execution of this program. However, when a program does not need this hazard checking, the microprocessor may execute this program in a mode where some portion of the hazard checking logic of the microprocessor may not be utilized in conjunction with the execution of this program. This allows the higher speed execution of these types of programs by eliminating checking for dependencies, the detection of false load/store dependencies, the insertion of unnecessary stalls into the execution pipeline of the microprocessor or other hardware operations. Furthermore, by reducing the use of hazard detection logic a decrease in power consumption may also be effectuated.

Abstract: Systems and methods for determining dependencies between processor instructions in multiple phases. In one embodiment, a partial comparison is made between the addresses of a sequence of instructions. Younger instructions having potential dependencies on older instructions are suspended if the partial comparison yields a match. One or more subsequent comparisons are made for suspended instructions based on portions of the addresses referenced by the instructions that were not previously compared. If subsequent comparisons determine that the addresses of the instructions do not match, the suspended instructions are reinstated and execution of the suspended instructions is resumed. In one embodiment, data needed by suspended instructions is speculatively requested in case the instructions are reinstated.

Abstract: Systems and methods for performing design verification testing in which test cases are analyzed to determine the characteristics that will be verified in a module under test, and in which the identified characteristics are used to selectively enable checker modules needed to verify the characteristics implicated by the test cases, while disabling other checker modules. In one embodiment, a system includes a test case analyzer and a checker selector. The test case analyzer analyzes one or more test cases and identifies test case characteristics that are associated with each of the test cases. The checker selector is coupled to the test case analyzer and receives identification of the test case characteristics from the test case analyzer. The checker selector then selectively enables a first set of design verification checkers and disables a second set, based on the test case characteristics identified for the test cases.