Patents by Inventor Kenji Kanbara
Kenji Kanbara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210320005Abstract: When a value obtained by dividing the number of the one or more second regions by a total of the number of the one or more first regions and the number of the one or more second regions is defined as a first defect free area ratio, a value obtained by dividing the number of the one or more fourth regions by a total of the number of the one or more third regions and the number of the one or more fourth regions is defined as a second defect free area ratio, and a value obtained by dividing the number of the one or more macroscopic defects by an area of the central region is defined as X cm?2, A is smaller than B, B is less than or equal to 4, X is more than 0 and less than 4, and a Formula 1 is satisfied.Type: ApplicationFiled: June 14, 2019Publication date: October 14, 2021Inventors: Kenji KANBARA, Hironori ITOH, Tsutomu HORI
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Patent number: 10526699Abstract: A silicon carbide epitaxial film has a plurality of arc-shaped or annular basal plane dislocations and a plurality of threading dislocations. The plurality of threading dislocations have a first threading dislocation which is surrounded by the plurality of basal plane dislocations and a second threading dislocation which is not surrounded by the plurality of basal plane dislocations, when viewed from a direction perpendicular to a main surface. The plurality of basal plane dislocations and the first threading dislocation constitute an annular defect. An area density of the plurality of threading dislocations in the main surface is more than or equal to 50 cm?2. A value obtained by dividing an area density of the annular defect when viewed from the direction perpendicular to the main surface by the area density of the plurality of threading dislocations in the main surface is more than or equal to 0.00002 and less than or equal to 0.004.Type: GrantFiled: July 20, 2018Date of Patent: January 7, 2020Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kenji Kanbara, Takaya Miyase, Tsubasa Honke
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Patent number: 10396163Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. The silicon carbide single crystal substrate has a first main surface. The silicon carbide layer is on the first main surface. The silicon carbide layer includes a second main surface opposite to a surface thereof in contact with the silicon carbide single crystal substrate. The second main surface has a maximum diameter of more than or equal to 100 mm. The second main surface includes an outer peripheral region which is within 3 mm from an outer edge of the second main surface, and a central region surrounded by the outer peripheral region. The central region has a haze of less than or equal to 75 ppm.Type: GrantFiled: August 4, 2016Date of Patent: August 27, 2019Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Wada, Hironori Itoh, Takemi Terao, Kenji Kanbara, Taro Nishiguchi
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Publication number: 20190242014Abstract: A silicon carbide epitaxial film has a plurality of arc-shaped or annular basal plane dislocations and a plurality of threading dislocations. The plurality of threading dislocations have a first threading dislocation which is surrounded by the plurality of basal plane dislocations and a second threading dislocation which is not surrounded by the plurality of basal plane dislocations, when viewed from a direction perpendicular to a main surface. The plurality of basal plane dislocations and the first threading dislocation constitute an annular defect. An area density of the plurality of threading dislocations in the main surface is more than or equal to 50 cm?2. A value obtained by dividing an area density of the annular defect when viewed from the direction perpendicular to the main surface by the area density of the plurality of threading dislocations in the main surface is more than or equal to 0.00002 and less than or equal to 0.004.Type: ApplicationFiled: July 20, 2018Publication date: August 8, 2019Inventors: Kenji KANBARA, Takaya MIYASE, Tsubasa HONKE
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Publication number: 20190019868Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. The silicon carbide single crystal substrate has a first main surface. The silicon carbide layer is on the first main surface. The silicon carbide layer includes a second main surface opposite to a surface thereof in contact with the silicon carbide single crystal substrate. The second main surface has a maximum diameter of more than or equal to 100 mm. The second main surface includes an outer peripheral region which is within 3 mm from an outer edge of the second main surface, and a central region surrounded by the outer peripheral region. The central region has a haze of less than or equal to 75 ppm.Type: ApplicationFiled: August 4, 2016Publication date: January 17, 2019Applicant: Sumitomo Electric Industries, Ltd.Inventors: Keiji Wada, Hironori Itoh, Takemi Terao, Kenji Kanbara, Taro Nishiguchi
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Patent number: 9966249Abstract: A silicon carbide semiconductor substrate includes a first main surface and a second main surface opposite to the first main surface. The first main surface has a maximum diameter of more than 100 mm, and the silicon carbide semiconductor substrate has a thickness of not more than 700 ?m. A dislocation density is not more than 500/mm2 at an arbitrary region having an area of 1 mm2 in a region within 5 mm from an outer circumferential end portion of the first main surface toward a center of the first main surface. Accordingly, there is provided a silicon carbide semiconductor substrate allowing for suppression of generation of cracks.Type: GrantFiled: August 11, 2014Date of Patent: May 8, 2018Assignee: Sumitomo Electric Industries, Ltd.Inventors: So Tanaka, Kyoko Okita, Taro Nishiguchi, Ryosuke Kubota, Kenji Kanbara
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Publication number: 20180005816Abstract: A semiconductor laminate includes a silicon carbide substrate having a first main surface and a second main surface opposite the first main surface, and an epitaxial layer composed of silicon carbide disposed on the first main surface. The second main surface has an average value of roughness Ra of 0.1 ?m or more and 1 ?m or less with a standard deviation of 25% or less of the average value.Type: ApplicationFiled: June 23, 2015Publication date: January 4, 2018Inventors: Kenji Kanbara, Keiji Wada, Tsubasa Honke
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Patent number: 9559217Abstract: A silicon carbide semiconductor device includes a silicon carbide layer, an insulating layer, a Schottky electrode, and a reaction region. The silicon carbide layer includes a p type region in contact with a first main surface and an n type region in contact with the p type region and the first main surface. The insulating layer has a third main surface, a fourth main surface, and a side wall surface connecting the third main surface and the fourth main surface, and is in contact with the first main surface at the fourth main surface. The Schottky electrode is in contact with the first main surface and the side wall surface. The reaction region is in contact with the insulating layer, the Schottky electrode, and the p type region. The reaction region contains an element constituting the Schottky electrode, an element constituting the insulating layer, silicon, and carbon.Type: GrantFiled: April 2, 2014Date of Patent: January 31, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Wada, Kenji Kanbara
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Publication number: 20160233080Abstract: A silicon carbide semiconductor substrate includes a first main surface and a second main surface opposite to the first main surface. The first main surface has a maximum diameter of more than 100 mm, and the silicon carbide semiconductor substrate has a thickness of not more than 700 ?m. A dislocation density is not more than 500/mm2 at an arbitrary region having an area of 1 mm2 in a region within 5 mm from an outer circumferential end portion of the first main surface toward a center of the first main surface. Accordingly, there is provided a silicon carbide semiconductor substrate allowing for suppression of generation of cracks.Type: ApplicationFiled: August 11, 2014Publication date: August 11, 2016Applicants: Sumitomo Electric Industries, Ltd., Sumitomo Electric Industries, Ltd.Inventors: So Tanaka, Kyoko Okita, Taro Nishiguchi, Ryosuke Kubota, Kenji Kanbara
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Publication number: 20160093749Abstract: A silicon carbide semiconductor device includes a silicon carbide layer, an insulating layer, a Schottky electrode, and a reaction region. The silicon carbide layer includes a p type region in contact with a first main surface and an n type region in contact with the p type region and the first main surface. The insulating layer has a third main surface, a fourth main surface, and a side wall surface connecting the third main surface and the fourth main surface, and is in contact with the first main surface at the fourth main surface. The Schottky electrode is in contact with the first main surface and the side wall surface. The reaction region is in contact with the insulating layer, the Schottky electrode, and the p type region. The reaction region contains an element constituting the Schottky electrode, an element constituting the insulating layer, silicon, and carbon.Type: ApplicationFiled: April 2, 2014Publication date: March 31, 2016Inventors: Keiji Wada, Kenji Kanbara
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Publication number: 20140061670Abstract: A wide gap semiconductor device has a substrate and a Schottky electrode. The substrate is made of a wide gap semiconductor material and has a first conductivity type. The Schottky electrode is arranged on the substrate to be in contact therewith and is made of a single material. The Schottky electrode includes a first region having a first barrier height and a second region having a second barrier height higher than the first barrier height. The second region includes an outer peripheral portion of the Schottky electrode. Thus, a wide gap semiconductor device capable of achieving less leakage current and a method for manufacturing the same can be provided.Type: ApplicationFiled: July 22, 2013Publication date: March 6, 2014Applicant: Sumitomo Electric Industries, Ltd.Inventors: Keiji Wada, Kenji Kanbara
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Publication number: 20130341648Abstract: A first layer of a first conductivity type made of silicon carbide is formed. A second layer of a second conductivity type different from the first conductivity type positioned on the first layer, and a third layer of the first conductivity type positioned on the second layer are formed. The step of forming second and third layers includes the steps of performing impurity ion implantation, and performing heat treatment for activating impurities implanted by the impurity ion implantation. After the step of performing heat treatment, a trench having a side wall penetrating the third layer and the second layer and having a bottom reaching the first layer is formed. A gate insulating film to cover the side wall of the trench is formed. As a result, a silicon carbide semiconductor device having a low ON resistance is provided.Type: ApplicationFiled: May 23, 2013Publication date: December 26, 2013Applicant: Sumitomo Electric Industries, Ltd.Inventors: Yu Saitoh, Takeyoshi Masuda, Sou Tanaka, Kenji Hiratsuka, Mitsuru Shimazu, Kenji Kanbara
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Patent number: 6810797Abstract: A resin-encapsulation method of the present invention for electronic parts by a stencil printing, in which a resin filling opening in a stencil is filled with a resin while a squeegee is being moved over the stencil, is characterized in that elevation control of the squeegee is made in a finish printing process at a position close to an end portion of the resin filling opening on a squeegee movement terminal side so as to scrape the excess of the filing resin out of the resin filling opening.Type: GrantFiled: October 18, 2002Date of Patent: November 2, 2004Assignee: Toray Engineering Company, LimitedInventors: Kenji Kanbara, Kazuo Ando, Shiro Okada
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Publication number: 20030106443Abstract: A resin-encapsulation method of the present invention for electronic parts by a stencil printing, in which a resin filling opening in a stencil is filled with a resin while a squeezee is being moved over the stencil, is characterized in that elevation control of the squeezee is made in a finish printing process at a position close to an end portion of the resin filling opening on a squeezee movement terminal side so as to scrape the excess of the filing resin out of the resin filling opening.Type: ApplicationFiled: October 18, 2002Publication date: June 12, 2003Inventors: Kenji Kanbara, Kazuo Ando, Shiro Okada