Patents by Inventor Kenji Kawakita

Kenji Kawakita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5175818
    Abstract: A communication system including a communication control unit connected through a communication line to a different system, a high-ranking processor for control of the communication control unit, and a common memory used for transfer of data between the high-ranking processor and the communication control unit. The communication control unit includes a direct memory access controller and a line controller interconnected via a transmission-only path and a reception-only path. The communication control unit autonomously generates an information frame and stores it in the common memory. The direct memory access controller then reads the information frame and transfers it to the line controller via the transmission-only path in order to transmit the information frame to the different system.
    Type: Grant
    Filed: February 21, 1989
    Date of Patent: December 29, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Masao Kunimoto, Kenji Kawakita, Kenichi Kimura
  • Patent number: 5169494
    Abstract: The present invention provides a method of forming a fine pattern comprising the steps of forming on a semiconductor substrate an organic polymer film and heat treating it, forming on the organic polymer film an inorganic film and heat treating it, forming on the inorganic film an electron beam resist film and heat treating it, drawing a pattern on the resist film, developing it to form a resist pattern, and etching the inorganic film and the organic polymer film using the resist pattern as a mask, wherein the improvement comprises using one substance selected from the group consisting of a polyphenylene sulfide, a derivative thereof, and a polymer represented by the formula (I): ##STR1## where n is a positive integer, for forming at least one of the organic polymer film and the electron beam resist film.
    Type: Grant
    Filed: August 8, 1991
    Date of Patent: December 8, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Hashimoto, Taichi Koizumi, Kenji Kawakita, Noboru Nomura
  • Patent number: 5119369
    Abstract: In a packet network which includes a plurality of packet switching stations and in which a packet including in its header portion a VPI (Virtual Path Indentifier) for identifying one of logical paths multipliexed on a transmission line and a VCI (Virtual Connection Identifier) for identifying one of logical connections multiplexed on one logical path is communicated between the switching stations, each switching station preliminarily designates a VCI to be given to a packet directed to that station when a logical connection is to be set up between that station and another station. When receiving an information packet from the other station, the each station makes access to header label conversion tables on the basis of a VCI included in the received packet to read internal routing information necessary for a packet switching operation and a VCI to be given to a packet to be delivered.
    Type: Grant
    Filed: July 3, 1990
    Date of Patent: June 2, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Shirou Tanabe, Kenji Kawakita, Shinobu Gohara
  • Patent number: 5093224
    Abstract: A process for forming a fine pattern comprising the steps of forming an organic polymer film on a semiconductor substrate followed by heat treatment, applying a resist film consisting of a cyclocarbosilane represented by the general formula (I): ##STR1## where R.sub.1, R.sub.2, R.sub.3 and R.sub.4 are each hydrogen or an alkyl group,a polymer resin, and a photo acid generator, on the organic polymer film followed by heat treatment, exposing to an electric charged beam, forming a resist pattern by developing, and etching the organic polymer film while using the resist pattern as a mask. According to the present invention, a dry etching resistant precise fine resist pattern can be formed with high sensitivity.
    Type: Grant
    Filed: March 20, 1990
    Date of Patent: March 3, 1992
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Hashimoto, Kenji Kawakita, Noboru Nomura
  • Patent number: 5090011
    Abstract: A packet switching equipment housing therein a plurality of pairs of an input line and an output line is provided with a monitor circuit for monitoring a packet congestion state in the packet switching equipment for each output line. When a packet congestion is detected in association with either one of the output lines, a congestion indicator is added to a packet to be delivered to the output line so as to return the packet as a congestion notice packet to an equipment as the transmission source of the packet; furthermore, the input packet is relayed via the output line to the destination equipment.
    Type: Grant
    Filed: December 21, 1989
    Date of Patent: February 18, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Isao Fukuta, Kenji Kawakita, Jiro Kashio, Yutaka Torii, Shinobu Gohara, Noboru Endo
  • Patent number: 5030549
    Abstract: Provided is a method for forming fine pattern free from shear of pattern caused by charging and high in dry etch resistance by using a high molecular organic film containing an organometallic complex or a metallic salt in single-layer or multi-layer resist process and treating the surface of this film with a reducing agent to form a metallic layer on the surface.
    Type: Grant
    Filed: June 26, 1989
    Date of Patent: July 9, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Hashimoto, Taichi Koizumi, Kenji Kawakita, Noboru Nomura
  • Patent number: 4998020
    Abstract: In formation of a fine pattern with direct electron beam delineation, disclosed is a method of obtaining parameters on an electron scattering intensity distribution expressed with a double Gaussian distribution obtained when exposing a resist with an electron beam. A resist on a substrate is exposed with an electron beam in accordance with an evaluation pattern which comprises a plurality of basic checked patterns each comprising longitudinal and lateral exposed stripes. The basic checked patterns are successively arranged longitudinally and laterally at predetermined intervals on a plane so as to form a plurality of longitudinal pattern rows and lateral pattern rows, widths of the stripes of the basic checked patterns in each of the lateral pattern rows being successively changed so as to be different from each other.
    Type: Grant
    Filed: March 28, 1990
    Date of Patent: March 5, 1991
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Akio Misaka, Kenji Kawakita, Kenji Harafuji, Hiromitsu Hamaguchi
  • Patent number: 4976818
    Abstract: A fine pattern forming method capable of forming an accurate fine pattern without charge-up at the time of electron beam or focus ion beam exposure, by treating the bottom layer or intermediate layer or silicon containing resist of a multi-layer resist with ion shower irradiation or reducing solvent.
    Type: Grant
    Filed: April 24, 1990
    Date of Patent: December 11, 1990
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Hashimoto, Taichi Koizumi, Kenji Kawakita, Noboru Nomura
  • Patent number: 4973684
    Abstract: Broad spectrum antibiotics are provided which are compounds of the formula: ##STR1## wherein R.sup.4 is a residue of a nucleophilic compound and R.sup.5 is hydroxyl or protected hydroxyl; or a pharmaceutically acceptable salt or ester thereof.
    Type: Grant
    Filed: June 7, 1988
    Date of Patent: November 27, 1990
    Assignee: Takeda Chemical Industries, Ltd.
    Inventors: Michihiko Ochiai, Taiiti Okada, Osamu Aki, Akira Morimoto, Kenji Kawakita, Yoshihiro Matsushita
  • Patent number: 4936951
    Abstract: A fine pattern forming method capable of forming an accurate fine pattern without charge-up at the time of electron beam or focus ion beam exposure is provided by treating the bottom layer or intermediate layer or silicon containing resist of a multi-layer resist with ion shower irradiation or reducing solvent.
    Type: Grant
    Filed: October 26, 1988
    Date of Patent: June 26, 1990
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuhiko Hashimoto, Taichi Koizumi, Kenji Kawakita, Noboru Nomura
  • Patent number: 4912212
    Abstract: Broad spectrum antibiotics are provided which are compounds of the formula: ##STR1## wherein -W-R is a residue of a nucleophilic compound and R.sup.5 is hydroxyl or protected hydroxyl, or a pharmaceutically acceptable salt or 4-carboxy ester which is the alkoxymethyl, .alpha.-alkoxyethyl, .alpha.-alkoxy-.alpha.-substituted methyl, alkylthiomethyl, acyloxymethyl or .alpha.-acyloxy-.alpha.-substituted methyl ester thereof.
    Type: Grant
    Filed: June 7, 1988
    Date of Patent: March 27, 1990
    Assignee: Takeda Chemical Industries, Ltd.
    Inventors: Michihiko Ochiai, Taiiti Okada, Osamu Aki, Akira Morimoto, Kenji Kawakita, Yoshihiro Matsushita
  • Patent number: 4881167
    Abstract: A data memory system includes a plurality of buffer regions each having a constant size so that serial data may be stored by linking the buffer regions. A descripter provided to correspond to each of the buffer regions includes memory region addressing information indicating the head address of the corresponding buffer region, data delimiting information indicating whether or not the data to be stored is terminated in the corresponding buffer region, and chain information indicating the head address of a next subsequent descripter.
    Type: Grant
    Filed: March 2, 1989
    Date of Patent: November 14, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Hisao Sasaki, Matsuaki Terada, Susumu Matsui, Kenji Kawakita, Jiro Kashio, Shiro Baba, Yasushi Akao, Toshio Okochi
  • Patent number: 4855995
    Abstract: Herein disclosed is a data communication system in which a plurality of node equipments are linked to a common signal transmission line so that the data may be communicated between the respective node equipments. The data communication system is characterized: in that at least one of the node equipments includes means for generating and transmitting repeatedly for a predetermined period the channel which contains a data transmission bit and a validity bit for the former bit; and in that each of the node equipments linked to the common signal transmission line partly sends out the data through said channel and partly makes the validity indicating bit indicate an invalid state, when the speed of said data is so slower than the predetermined period of said channel that the data to be sent out for the predetermined period are out of time thereby to make it possible to effect the data transmission at an arbitrary speed shorter than said predetermined period.
    Type: Grant
    Filed: January 27, 1987
    Date of Patent: August 8, 1989
    Assignee: Hitachi, Ltd.
    Inventors: Kunio Hiyama, Kenji Kawakita, Osamu Takada
  • Patent number: 4814287
    Abstract: A method of manufacturing a semiconductor integrated circuit device of the bipolar type of the MOS type or an integration of the two types having high integration and high performance, in which the circuit includes a first device region of which the side surface and entire region of the lower portion of the active region are made of silicon oxide and a second device region of which the side surface and a part of the lower portion of the active region are made of silicon oxide. According to the present invention, a transistor whose bottom portion is opened and a transistor whose bottom portion is not opened can be freely provided on a substrate, thereby dividing the transistors into a transistor to which a voltage can be supplied from the substrate and a transistor to which the voltage can not be supplied from the substrate, so that the wiring which has been conventionally needed can be reduced.
    Type: Grant
    Filed: August 6, 1987
    Date of Patent: March 21, 1989
    Assignee: Matsushita Electric Industrial Co. Ltd.
    Inventors: Toyoki Takemoto, Kenji Kawakita, Hiroyuki Sakai
  • Patent number: 4685198
    Abstract: Disclosed is a method of isolating a transistor perfectly by employing a selective oxidation technology (LOCOS technology). More particularly, vertical openings are formed in the surface of {100} silicon substrate, and oxidation resistant films are formed of this surface and in part of the side walls of these openings. In succession, by etching with an etchant having an orientation anisotropy, dents are formed at high precision in the side walls of the openings. By oxidizing using the oxidation resistant film as the mask, an oxide film growing out from a dent in the opening side wall is connected with another oxide film growing out from an adjacent dent. The transistor thus formed in the active region of the silicon electrically isolated from the substrate is small in parasitic capacitance and may be formed into a small size, so that it possesses the features suited to VLSI, that is, high speed, low power consumption, and processability to high density integration.
    Type: Grant
    Filed: July 25, 1985
    Date of Patent: August 11, 1987
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kenji Kawakita, Noboru Nomura, Toyoki Takemoto
  • Patent number: 4668783
    Abstract: Novel cephem compounds of the formula: ##STR1## wherein R.sup.4 is a residue of a nucleophilic compound selected from hydroxyl, mercapto, cyano, azido, amino, carbamoyloxy, carbamoylthio and thiocarbamoyloxy, said group being unsubstituted or substituted by alkyl of up to three carbons, and R.sup.5 is hydroxyl or lower alkoxy, or a pharmaceutically acceptable ester thereof, have strong antibiotic properties against a wide variety of microorganisms.
    Type: Grant
    Filed: January 23, 1986
    Date of Patent: May 26, 1987
    Assignee: Takeda Chemical Industries, Ltd.
    Inventors: Michihiko Ochiai, Taiiti Okada, Osami Aki, Akira Morimoto, Kenji Kawakita, Yoshihiro Matsushita
  • Patent number: 4615746
    Abstract: A method of fabricating a semiconductor device comprises the steps of forming oxidation-resistive films on the surface and sides of a protrusion formed on a semiconductor substrate, forming grooves at the bottom of the sides of the protrusion, forming highly doped impurity diffusion regions in the groove surfaces, and subjecting the grooves to selective oxidation to form an oxide film under the bottom of the protrusion while a highly doped impurity diffusion region is formed, and forming a device in the protrusion.
    Type: Grant
    Filed: September 19, 1984
    Date of Patent: October 7, 1986
    Inventors: Kenji Kawakita, Hiroyuki Sakai, Toyoki Takemoto
  • Patent number: 4563807
    Abstract: Semiconductor device, such as bipolar transistor, is made by molecular beam epitaxy, wherein a emitter layer (27) and overriding contact regions (28) of polycrystalline silicon are grown continuously on a silicon substrate (23+26) without breaking high vacuum, thus eliminating the adverse interface of natural oxide film under the polycrystalline silicon layer (28) and the adverse donor-acceptor compensation while attaining a well controlled h.sub.FE and enabling a shallow emitter junction.
    Type: Grant
    Filed: April 4, 1984
    Date of Patent: January 14, 1986
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Sakai, Toyoki Takemoto, Kenji Kawakita, Tsutomu Fujita, Atsuko Akiyama
  • Patent number: 4563227
    Abstract: The invention provides a method for manufacturing a semiconductor device, wherein a semiconductor substrate is vertically etched to form a groove, antioxidant insulating films are formed on the side walls of the groove, and local oxidation is performed. Lateral extrusion of an oxide film which is a so-called bird's beak and a projection of the oxide film which is a so-called bird's head are substantially eliminated. As a result, the active region of the transistor, that is, the element formation region may not be narrowed, providing high packing density and high precision. Furthermore, the surface of the semiconductor substrate is flattened to prevent short-circuiting and disconnections of wiring layers. Stable manufacturing process provides a high yield of the semiconductor device. Electrical characteristics of the semiconductor device are greatly improved.
    Type: Grant
    Filed: October 12, 1984
    Date of Patent: January 7, 1986
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Sakai, Kenji Kawakita, Tsutomu Fujita, Toyoki Takemoto
  • Patent number: 4514565
    Abstract: 3-Tertiary ammoniomethyl-7-beta-[alpha-(hydroxy or protected hydroxy)imino-alpha-(2-aminothiazol-4-yl)acetamido]-3-cephem-4-carboxylic acid, pharmaceutically acceptable salt or 4-carboxy ester is provided which is a broad spectrum antibiotic.
    Type: Grant
    Filed: June 24, 1983
    Date of Patent: April 30, 1985
    Assignee: Takeda Chemical Industries, Ltd.
    Inventors: Michihiko Ochiai, Taiiti Okada, Osami Aki, Akira Morimoto, Kenji Kawakita, Yoshihiro Matsushita