Patents by Inventor Kenji Kigima

Kenji Kigima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Package for semiconductor power device and method for assembling the same
    Patent number: 6597063
    Abstract: A package for a semiconductor power device which comprises: a conductive bottom plate as a heat sink; an insulating substrate mounted on the bottom plate; a copper film formed on the insulating substrate to expose a peripheral region of the insulating substrate; semiconductor chips disposed on the copper film; a container arranged on the bottom plate, surrounding the insulating substrate; an external terminal supported through the container and connected electrically with the semiconductor chips; and a silicone gel filled within the container, wherein a solidified insulating material is disposed on an outer edge region of the copper film and the peripheral region of the insulating substrate. Thus, reducing an electric field across the interface and making it difficult to cause a creeping discharge. A notch is formed in the bottom plate, and the notch is filled with a high heat conductive resin. The notch is located outwardly apart from a region where the semiconductor chips are mounted.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: July 22, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshio Shimizu, Hiroyuki Hiramoto, Hiroki Sekiya, Kenji Kigima
  • Package for semiconductor power device and method for assembling the same
    Patent number: 6201696
    Abstract: A package for a semiconductor power device which comprises: a conductive bottom plate as a heat sink; an insulating substrate mounted on the bottom plate; a copper film formed on the insulating substrate to expose a peripheral region of the insulating substrate; semiconductor chips disposed on the copper film; a container arranged on the bottom plate, surrounding the insulating substrate; an external terminal supported through the container and connected electrically with the semiconductor chips; and a silicone gel filled within the container, wherein a solidified insulating material is disposed on an outer edge region of the copper film and the peripheral region of the insulating substrate. Thus, reducing an electric field across the interface and making it difficult to cause a creeping discharge. A notch is formed in the bottom plate, and the notch is filled with a high heat conductive resin. The notch is located outwardly apart from a region where the semiconductor chips are mounted.
    Type: Grant
    Filed: December 8, 1998
    Date of Patent: March 13, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshio Shimizu, Hiroyuki Hiramoto, Hiroki Sekiya, Kenji Kigima