Abstract: An electric power steering device includes a phase advance correction unit configured to advance a phase of a steering torque signal detected by a torque sensor detecting a steering torque input from a steering wheel, a specific frequency extraction unit configured to extract a component in a specific frequency band out of the steering torque signal detected by the torque sensor, a gain multiplication unit configured to correct a steering torque signal computed on the basis of an output signal of the phase advance correction unit and an output signal of the specific frequency extraction unit such that the steering torque signal reaches a limit value set by a limiter by multiplying the steering torque signal by a gain, and an addition unit configured to add an assist correction command value calculated on the basis of an output signal output from the gain multiplication unit to the assist command value.

Abstract: An electric power steering device includes a phase advance correction unit configured to advance a phase of a steering torque signal detected by a torque sensor detecting a steering torque input from a steering wheel, a specific frequency extraction unit configured to extract a component in a specific frequency band out of the steering torque signal detected by the torque sensor, a gain multiplication unit configured to correct a steering torque signal computed on the basis of an output signal of the phase advance correction unit and an output signal of the specific frequency extraction unit such that the steering torque signal reaches a limit value set by a limiter by multiplying the steering torque signal by a gain, and an addition unit configured to add an assist correction command value calculated on the basis of an output signal output from the gain multiplication unit to the assist command value.

Abstract: In a buffer memory device intermediate between a data processing unit and a main memory to memorize and read out an operand data block and an instruction data block in response to an operand request and an instruction request, respectively, the operand and the instruction data blocks have an operand block size and an instruction block size equal to N times the operand block size, respectively, where N is an integer greater than unity. The number N is preferably equal to 2.sup.n, where n is a natural number. The buffer memory device comprises a data buffer having a plurality of cache areas each of which has a predetermined area size equal to the operand block size. Thus, the operand data block occupies a single one of the cache areas while the instruction data block occupies a plurality of the cache areas, N in number. The operand data blocks coexist with the instruction data blocks in the data buffer at different block sizes.