Patents by Inventor Kenji Ohsawa
Kenji Ohsawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6051450Abstract: Metal films (for instance, gold films or palladium films) to constitute bumps are formed on a metal base by electrolytic plating. Then, a circuit wiring including inner leads is formed by electrolytic plating with a metal so that the inner leads are connected to the respective metal films.Type: GrantFiled: June 30, 1998Date of Patent: April 18, 2000Assignee: Sony CorporationInventors: Kenji Ohsawa, Hidetoshi Kusano, Haruhiko Makino, Hideyuki Takahashi
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Patent number: 6020626Abstract: A semiconductor device is provided which can improve a heat radiation characteristic of the package, and also can solve an uniform characteristic of ball sizes when a projection electrode such as soldering balls is formed by way of the electrolytic plating method. A semiconductor device is comprised of: a semiconductor chip in having a plurality of electrode pads and an inside of a pad forming region thereof used as an effective element region; a reinforcement plate provided under such a condition that this semiconductor chip is surrounded by the reinforcement plate; a plurality of leads constituted by an outer lead and an inner lead, in which a projection electrode is provided on the outer lead, and also a tip portion of the inner lead is connected to the electrode pads sealing resin filled into a peripheral region of the semiconductor chip.Type: GrantFiled: September 18, 1998Date of Patent: February 1, 2000Assignee: Sony CorporationInventors: Kenji Ohsawa, Tomoshi Ohde
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Patent number: 5982033Abstract: According to a method of manufacturing a semiconductor package of the present invention, a plurality of leads and a large number of minute convex portions are respectively formed by plating on a surface of a metal base and in an outer peripheral area of the leads thereon. An insulative film for holding each of the leads is formed. A solder resist film is formed selectively on a portion including the outer peripheral area having the minute convex portions thereon. A projecting electrode is formed on an outer lead portion of each of the leads through an opening of the solder resist film on an outer lead portion of each of the leads. The metal base is selectively removed except a joint portion thereof on an outer periphery to separate the respective leads. Inner lead portions of the leads and a semiconductor chip are jointed together. The joint portion of the metal base is cut off.Type: GrantFiled: May 2, 1997Date of Patent: November 9, 1999Assignee: Sony CorporationInventors: Kenji Ohsawa, Makoto Ito
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Patent number: 5945741Abstract: A semiconductor device employs interconnecting films on film circuit as ground lines which extend to the periphery of the film circuit where there is a further connection to a conductive reinforcing plate. Advantageously the conductive reinforcing plate reduces electrical noise from interfering with the semiconductor device and prevents the semiconductor device from radiating undesired signals. The interconnecting films also reduce cross-talk between signal lines of the semiconductor device.Type: GrantFiled: March 5, 1997Date of Patent: August 31, 1999Assignee: Sony CorporationInventors: Kenji Ohsawa, Makoto Ito, Yasushi Otsuka, Kazuhiro Sato
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Patent number: 5937278Abstract: A method of manufacturing a lead frame comprises the steps of preparing a three-layered material comprising a metal base, an etching stopper layer made of a metal material different from that of the metal layer formed on a first surface of the metal base and a chromium layer formed on the etching stopper layer, forming a resist layer having a negative pattern relative to an inner lead to be formed on the chromium layer of the three-layered material, forming an inner lead by plating copper by using the resist layer as a mask, forming an outer lead on the metal base, removing a back of a region in which an inner lead of the metal base is formed by etching, removing the etching stopper layer, and removing the chromium layer.Type: GrantFiled: October 15, 1996Date of Patent: August 10, 1999Assignee: Sony CorporationInventors: Makoto Ito, Kenji Ohsawa, Mutsumi Nagano
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Patent number: 5901436Abstract: Leads are formed on a surface of an etching stop film of a base, and holes are defined in the base and a region of a substrate which corresponds to a lead-forming region is thinned by selective etching on both upper and lower surfaces of the base. A lead holder film having a device hole and an outer lead bonding slit is applied to the upper surface of the base. The thinned region of the substrate is removed by selective etching on the lower surface of the base, and the etching stop film is etched away.Type: GrantFiled: October 16, 1996Date of Patent: May 11, 1999Assignee: Sony CorporationInventors: Kenji Ohsawa, Makoto Ito
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Patent number: 5886399Abstract: A lead frame includes a plurality of leads held by an insulative holding film and each formed of an inner lead portion for being bonded to a semiconductor chip and an outer lead portion, a pad portion formed at an end portion of the outer lead portion, an insulating film formed in a pattern so as to insulate the adjacent leads, a ground film formed on the pad portion and partially on the insulating film and having a wider area as compared with that of the pad portion, and a projecting electrode formed on the ground film.Type: GrantFiled: September 18, 1996Date of Patent: March 23, 1999Assignee: Sony CorporationInventors: Kenji Ohsawa, Makoto Ito
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Patent number: 5786239Abstract: According to a method of manufacturing a semiconductor package of the present invention, a plurality of leads and a large number of minute convex portions are respectively formed by plating on a surface of a metal base and in an outer peripheral area of the leads thereon. An insulative film for holding each of the leads is formed. A solder resist film is formed selectively on a portion including the outer peripheral area having the minute convex portions thereon. A projecting electrode is formed on an outer lead portion of each of the leads through an opening of the solder resist film on an outer lead portion of each of the leads. The metal base is selectively removed except a joint portion thereof on an outer periphery to separate the respective leads. Inner lead portions of the leads and a semiconductor chip are jointed together. The joint portion of the metal base is cut off.Type: GrantFiled: September 20, 1996Date of Patent: July 28, 1998Assignee: Sony CorporationInventors: Kenji Ohsawa, Makoto Ito
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Patent number: 5756377Abstract: In a lead frame, leads are formed on a surface of protective insulation film having a device hole. Protruding electrodes (solder balls) are formed on the surface of the leads opposite the surface closer to the protective insulation film. A reinforcement plate is also formed on the rear surface of the protective insulation film.Type: GrantFiled: December 12, 1996Date of Patent: May 26, 1998Assignee: Sony CorporationInventor: Kenji Ohsawa
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Patent number: 5723900Abstract: A ultra thin resin mold semiconductor device can be provided. A resin mold type semiconductor device is arranged so that a semiconductor chip is disposed within a range of the thickness of a lead frame and sealed with a resin mold, that the thickness of the semiconductor device is defined by the thickness of the lead frame, and that an upper surface, a lower surface and a side surface of a terminal portion formed by the lead frame are exposed from the surface of the resin mold.Type: GrantFiled: February 12, 1997Date of Patent: March 3, 1998Assignee: Sony CorporationInventors: Akira Kojima, Haruhiko Makino, Kenji Ohsawa
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Patent number: 5481798Abstract: A lead frame capable of easily connecting an inner lead to an electrode of a semiconductor element by way of a bump of the inner lead, and a method of manufacturing the lead frame capable of significantly easily forming the bump. A bump forming metal layer is formed on a metal base sheet on an area where each inner lead is to be formed. The inner lead is formed on the bump forming metal layer, and the bump forming metal layer is etched using the inner lead as a mask, thus forming a bump. After that, each outer lead is formed by selective etching of the metal base sheet from the rear surface side.Type: GrantFiled: January 13, 1995Date of Patent: January 9, 1996Assignee: Sony CorporationInventors: Kenji Ohsawa, Makoto Ito, Mutsumi Nagano
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Patent number: 5437764Abstract: An inner lead of a lead frame has an outer end portion extending so as to be connected with a side surface of an etching stop layer and with an upper surface of an outer lead. The outer lead is formed by etching both surfaces of a metal base, and the inner lead is formed by plating metal on the metal base with a resist layer used as a mask. The pitch of the outer lead can be made fine, and a bonding strength of the inner lead to the outer lead can be increased.Type: GrantFiled: May 24, 1994Date of Patent: August 1, 1995Assignee: Sony CorporationInventors: Kenji Ohsawa, Makoto Ito, Mutsumi Nagano
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Patent number: 5349238Abstract: Disclosed is a semiconductor device comprising a lead frame which includes a metal layer forming an outer lead, a thin metal layer forming an inner lead, an intermediate layer held between the thick metal layer and the thin metal layer for forming a connection portion between the outer lead and the inner lead and a bump positioned at the extreme end of the lead frame, whereby making the lead frame as an electrode leading means by directly connecting the bump to each electrode of a semiconductor element, wherein the lead formed of the thick metal layer has a thickness of 30 to 300 .mu.m, the lead formed of the thin metal layer has a thickness of 10 to 50 .mu.m, and the bump has thickness of 5 to 50 .mu.m.Type: GrantFiled: September 23, 1992Date of Patent: September 20, 1994Assignee: Sony CorporationInventors: Kenji Ohsawa, Mutsumi Nagano, Akira Kojima, Hideyuki Takahashi
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Patent number: 5221428Abstract: A method for producing a lead frame which comprises selectively forming a photoresist film on both sides of a lead frame material of three-layered structure, with an etching stop layer interposed between two metal layers, etching both sides thereof using the photoresist film as a mask, and removing the unnecessary part of the etching stop layer.Type: GrantFiled: September 6, 1991Date of Patent: June 22, 1993Assignee: Sony CorporationInventors: Kenji Ohsawa, Akira Kojima, Hideyuki Takahashi
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Patent number: 4677252Abstract: A circuit board comprises a rigid metal substrate, a conductive metal layer formed into a predetermined circuit pattern, and a resinous layer interposed between the metal substrate and the metal layer for electrically insulating and bonding the metal substrate and the metal layer, the conductive metal layer having an elongation at break of not less than 15%, and the resinous layer comprising a first resinous layer having a volume resistivity of not less than 10.sup.10 .OMEGA.. cm, and a second resinous layer having an elongation at break of not less than 100%. The circuit board has a desired dielectric strength between the metal substrate and the conductive metal layer and can be bent without resulting disconnection in the metal layer or the like.Type: GrantFiled: November 18, 1986Date of Patent: June 30, 1987Assignee: Sony CorporationInventors: Satoshi Takahashi, Akira Tsutsumi, Junji Suzuki, Hiroshi Kumakura, Takao Ito, Kenji Ohsawa, Yuji Ikegami, Muneyuki Haruki, Nobuyuki Yasuda, Masayuki Ohta
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Patent number: 4528064Abstract: A multilayer circuit board provided with multilayer wiring patterns as upper and lower multilayers is provided, in which on a first circuit board 24 with a first wiring pattern 23 formed thereon a copper foil 27 is bonded through an insulating resin layer 25, the patterning is carried out so as to form a second wiring pattern 33, and the upper and lower patterns 23 and 33 are connected to each other by conductive substance 34 filled within an opening portion 32 of the second wiring pattern 33. In accordance with this multilayer circuit board, the quality thereof is improved, the manufacturing thereof is carried out at low cost, and in addition, it becomes possible to form a circuit of high density integration.Type: GrantFiled: November 13, 1984Date of Patent: July 9, 1985Assignee: Sony CorporationInventors: Kenji Ohsawa, Takao Ito, Masayuki Ohsawa, Keiji Kurata
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Patent number: 4435611Abstract: A novel conductive paste is disclosed which is suitable for use to connect circuit patterns of a printed circuit board.The conductive paste comprises a melt of gallium and a metal element which forms an eutectic mixture with gallium, and metal powder which alloys with gallium uniformly dispersed in the melt. The content of the metal element and the metal powder are selected to control a solid content in the paste at a predetermined working temperature.Type: GrantFiled: December 23, 1982Date of Patent: March 6, 1984Assignee: Sony CorporationInventors: Kenji Ohsawa, Takao Ito, Shimetomo Fueki, Masayuki Osawa, Keiji Kurata
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Patent number: 4398975Abstract: A novel conductive paste and a method of making the same in which metallic gallium is combined with a metal or alloy which forms a eutectic with gallium in an amount in excess of its limit of solubility in gallium at a specific temperature. This melt is then treated with a metal powder of a second metal or alloy which alloys with gallium to produce a higher melting alloy, the second metal powder being coated on its surface with the eutectic-forming metal.Type: GrantFiled: December 16, 1981Date of Patent: August 16, 1983Assignee: Sony CorporationInventors: Kenji Ohsawa, Takao Ito, Koichiro Tanno, Masayuki Ohsawa, Keiji Kurata