Patents by Inventor Kenji Oota

Kenji Oota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11930798
    Abstract: A fishing rod includes a hollow rod extending along a central axis; and a shaft member with an outer peripheral surface inclined relative to the central axis inserted into the rod from the one end, and that is supported by an inner peripheral surface of the rod at a support position on another end side of the one end in an axial direction along the central axis, wherein the inner peripheral surface of the rod has at least one convex portion protruding toward the central axis from a virtual curve between the support position and the one end position axially when drawing a virtual curve that is convex toward the central axis through the support position and the one end position at the end of the end side of the inner peripheral surface in an area radially outward from the outer peripheral surface of the shaft member.
    Type: Grant
    Filed: October 25, 2019
    Date of Patent: March 19, 2024
    Assignee: Globeride, Inc.
    Inventors: Yasuhiro Tsukamoto, Atsushi Saito, Masayoshi Nakao, Kenji Kato, Isao Oota
  • Patent number: 8456001
    Abstract: A pressure-contact semiconductor device (100) includes thermal buffer plates (2) and main electrode blocks (3) having flanges (4), by which semiconductor substrate (1) having a pair of electrodes is sandwiched, disposed opposed to each side thereof, wherein the semiconductor substrate (1) is sealed in a gastight space by joining the flanges (4) to insulating container (5). The semiconductor device (100) is configured such that the outermost periphery of the semiconductor substrate (1) is enclosed by hollow cylindrical insulator (9) fitted on outer peripheries of the main electrode blocks (3) in the gastight space with O-rings (8) fitted between the main electrode blocks (3) and the cylindrical insulator (9), and sealed with reaction force from the O-rings (8).
    Type: Grant
    Filed: March 9, 2007
    Date of Patent: June 4, 2013
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kazunori Taguchi, Kenji Oota
  • Publication number: 20110250457
    Abstract: [PROBLEMS TO BE SOLVED] There are provided an in-mold coating composition having an excellent adhesion to a thermosetting molding resin or a thermoplastic molding resin and an in-mold-coated molded product formed by coating effectively with a conductive coating film in a mold. [SOLUTION] This invention is an in-mold coating composition characterized by comprising components of (A) at least one selected from a urethane oligomer, an epoxy oligomer, a polyester oligomer and a polyether oligomer each having a (meth)acryloyl group, or an unsaturated polyester resin, (B) a monomer capable of copolymerizing with the (A) component, (C) a conductive particle formed by coating a surface of an inorganic particle with a conductive metal oxide particle, and (D) an organic peroxide polymerization initiator, wherein mass ratios of the (A) and (B) components satisfy (A)/(B)=20/80-80/20, a mass ratio of the (C) component satisfies (C)/{(A)+(B)}=5/100-50/100, and a mass ratio of the (D) component satisfies (D)/{(A)+(B)}=0.
    Type: Application
    Filed: December 10, 2009
    Publication date: October 13, 2011
    Applicant: Dai Nippon Toryo Co., Ltd.
    Inventors: Kenji Oota, Shinichirou Shiroza, Kenji Yonemochi
  • Patent number: 7837918
    Abstract: An in-mold coating method providing a mold having a specifically formed auxiliary cavity and an in-mold coating formation method which employs said mold, so that it is possible to prevent a coating material from leaking out of the mold, thereby shortening the molding formation cycle, and making it possible to manufacture a molded product having a stabilized quality. In addition, by using a mold having a specifically shaped sub-cavity, there is provided a still further in-mold coating formation method which can keep mold temperature at a relatively low value, cause the coating material to cure at a predetermined temperature and within a predetermined time period thereby shortening the molding formation cycle, improving the productivity, improving the physical properties of a coating layer, thus obtaining a good molded product.
    Type: Grant
    Filed: October 6, 2008
    Date of Patent: November 23, 2010
    Assignees: Dai Nippon Toryo Co., Ltd., Ube Machinery Corporation, Ltd.
    Inventors: Kenji Yonemochi, Yoshiaki Yamamoto, Kenji Oota, Toshio Arai, Etsuo Okahara, Kazuaki Kobayashi
  • Patent number: 7832999
    Abstract: An in-mold coating apparatus providing a mold having a specifically formed auxiliary cavity and an in-mold coating formation method which employs said mold, so that it is possible to prevent a coating material from leaking out of the mold, thereby shortening the molding formation cycle, and making it possible to manufacture a molded product having a stabilized quality. In addition, by using a mold having a specifically shaped sub-cavity, there is provided a still further in-mold coating formation method which can keep mold temperature at a relatively low value, cause the coating material to cure at a predetermined temperature and within a predetermined time period thereby shortening the molding formation cycle, improving the productivity, improving the physical properties of a coating layer, thus obtaining a good molded product.
    Type: Grant
    Filed: November 17, 2005
    Date of Patent: November 16, 2010
    Assignees: Dai Nippon Toryo Co., Ltd., Ube Machinery Corporation, Ltd.
    Inventors: Kenji Yonemochi, Yoshiaki Yamamoto, Kenji Oota, Toshio Arai, Etsuo Okahara, Kazuaki Kobayashi
  • Patent number: 7790081
    Abstract: A process producing an in-mold coated molded product. The process molds a thermoplastic resin material under a mold-clamping pressure in a mold including a fixed mold part and a movable mold part each heated at a predetermined temperature, separates the fixed mold part and the movable mold part when the molded material surface is solidified such that it is durable to a pressure of injection and flow of a coating agent, and injects the coating agent containing a thermosetting resin material between an inner surface of the mold and the molded product obtained. The process also coats the molded product surface with the coating agent as the mold is re-clamped after injecting the coating agent, takes out the molded product coated with the coating agent when the coating agent is cured such that it is neither peeled off nor cracked by opening the mold, and re-heats the molded product after taking it out.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: September 7, 2010
    Assignees: Dai Nippon Toryo Co., Ltd., Ube Machinery Corporation, Ltd.
    Inventors: Kenji Oota, Kenji Yonemochi, Toshio Arai, Etuo Okahara, Kazuaki Kobayashi, Takashi Okusako
  • Publication number: 20090286054
    Abstract: Provided is a sheet for decoration which is excellent in an impact resistance in molding a surface form having a three-dimensional curved surface having a high deep-drawing degree and which has a good followability toward a molding surface of a metal die and is suited to decorated moldings. The above sheet for decoration comprises a peel layer, a picture layer and a heat adhesive resin layer which are laminated in order on the surface of a base film comprising a polyester film, wherein a dynamic elastic modulus of the above base film is 1.0×106 Pa or more at any temperature falling in a range of 190 to 240° C.
    Type: Application
    Filed: September 26, 2007
    Publication date: November 19, 2009
    Inventors: Yoshiyuki Meiki, Hiroyuki Atake, Kenji Oota
  • Publication number: 20090121385
    Abstract: By managing a coating material injection time and the like parameters so that they may be controlled within specifically determined ranges, an in-mold coating formation method is provided for manufacturing a molded product coated with a coating layer having a uniform quality in its outside appearance. By continuously and unifyingly managing a mold opening amount and a mold closing force, an in-mold coating formation method and an in-mold coating formation apparatus are provided which are so formed that, if the control of a mold closing force and the control of a mold opening amount are continuously changed and at the same time a high precision and a high response are maintained, it is possible to enlarge a selectable range for selecting a molding condition, thereby producing an integrally formed molded product having an excellent outside appearance and whose coating layer has a high adhesion strength.
    Type: Application
    Filed: October 6, 2008
    Publication date: May 14, 2009
    Applicants: Dai Nippon Toryo Co., Ltd., Ube Machinery Corporation, Ltd.
    Inventors: Kenji Yonemochi, Yoshiaki Yamamoto, Kenji Oota, Toshio Arai, Etsuo Okahara, Kazuaki Kobayashi
  • Patent number: 7482063
    Abstract: An in-mold coating molded article is obtained by coating the surface of a resin molded product comprising a hydroxyl group-containing polypropylene resin composition (A) with a paint composition for in-mold coating, wherein the composition (A) comprises a polypropylene resin (i), an additive rubber (ii) and optionally a polymer compound (iii) other than the polypropylene resin (i) and the additive rubber (ii), the total hydroxyl value of the polypropylene resin (i), the additive rubber (ii) and the optional polymer compound (iii) is from 1 to 40, the composition (A) has a rubber component content (total of the amount of the additive rubber (ii) and the amount of components soluble in n-decane at 23° C.
    Type: Grant
    Filed: August 21, 2003
    Date of Patent: January 27, 2009
    Assignees: Prime Polymer Co., Ltd., Dai Nippon Toryo Co., Ltd., Ube Machinery Corporation, Ltd.
    Inventors: Takeshi Minoda, Yuichi Matsuda, Kaoru Yorita, Kenji Yonemochi, Kenji Oota, Etsuo Okahara, Toshio Arai
  • Publication number: 20080073767
    Abstract: A pressure-contact semiconductor device (100) includes thermal buffer plates (2) and main electrode blocks (3) having flanges (4), by which semiconductor substrate (1) having a pair of electrodes is sandwiched, disposed opposed to each side thereof, wherein the semiconductor substrate (1) is sealed in a gastight space by joining the flanges (4) to insulating container (5). The semiconductor device (100) is configured such that the outermost periphery of the semiconductor substrate (1) is enclosed by hollow cylindrical insulator (9) fitted on outer peripheries of the main electrode blocks (3) in the gastight space with O-rings (8) fitted between the main electrode blocks (3) and the cylindrical insulator (9), and sealed with reaction force from the O-rings (8).
    Type: Application
    Filed: March 9, 2007
    Publication date: March 27, 2008
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Kazunori TAGUCHI, Kenji OOTA
  • Patent number: 7307289
    Abstract: A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N?-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: December 11, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiro Yamaguchi, Kenji Oota
  • Patent number: 7301178
    Abstract: A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N?-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: November 27, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yoshihiro Yamaguchi, Kenji Oota
  • Patent number: 7244969
    Abstract: A power semiconductor device comprises a semiconductor substrate, a gate electrode region (control electrode region), a cathode electrode region (first main electrode region), an anode electrode region (second main electrode region) and a guard ring. The semiconductor substrate has a side surface portion having a vertical portion formed substantially vertical to a main surface and a mesa portion connected to the vertical portion in a cross section. The gate electrode region is formed in a first main surface of the semiconductor substrate. The cathode electrode region is formed in part of a surface of the gate electrode region. The anode electrode region is formed in a second main surface of the semiconductor substrate. The guard ring is formed in the second main surface of the semiconductor substrate and annularly surrounds the anode electrode region.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: July 17, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenji Oota, Yoshihiro Yamaguchi, Hiroshi Yamaguchi
  • Patent number: 7221047
    Abstract: A gate electrode (1a) is formed on the outer peripheral step portion (1?) of a semiconductor substrate (1) so as to face a pressure-contact supporting block (6), and a convex contacting portion (1g) is formed on a predetermined position on the surface of the gate electrode to contact the pressure contact supporting block. The surface area of the gate electrode ranging from the inner periphery to a position adjacent to the convex contacting portion, is coated with an insulation film (1d). The convex contacting portion (1g) is formed of a convex portion integral with the gate electrode or formed of another gate electrode (1a?).
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: May 22, 2007
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenji Oota, Futoshi Tokunoh
  • Patent number: 7100547
    Abstract: An intake-air control system for an engine enabling an intake-air quantity and a compression ratio to be variably controlled, includes sensors detecting engine operating conditions and the compression ratio, and a control unit electronically connected to the sensors for feedback-controlling the intake-air quantity based on the compression ratio as well as the engine operating conditions, while feedback-controlling the compression ratio based on the engine operating conditions. The control unit executes phase-matching between an intake-air quantity change occurring based on intake-air quantity control and a compression ratio change occurring based on compression ratio control, considering a relatively slower response in the compression ratio change than a response in the intake-air quantity change.
    Type: Grant
    Filed: November 19, 2003
    Date of Patent: September 5, 2006
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Kensuke Osamura, Hiroshi Iwano, Kenji Oota
  • Publication number: 20060151805
    Abstract: A power semiconductor device comprises a semiconductor substrate, a gate electrode region (control electrode region), a cathode electrode region (first main electrode region), an anode electrode region (second main electrode region) and a guard ring. The semiconductor substrate has a side surface portion having a vertical portion formed substantially vertical to a main surface and a mesa portion connected to the vertical portion in a cross section. The gate electrode region is formed in a first main surface of the semiconductor substrate. The cathode electrode region is formed in part of a surface of the gate electrode region. The anode electrode region is formed in a second main surface of the semiconductor substrate. The guard ring is formed in the second main surface of the semiconductor substrate and annularly surrounds the anode electrode region.
    Type: Application
    Filed: August 2, 2005
    Publication date: July 13, 2006
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Kenji Oota, Yoshihiro Yamaguchi, Hiroshi Yamaguchi
  • Publication number: 20060076712
    Abstract: By managing a coating material injection time and the like parameters so that they may be controlled within specifically determined ranges, an in-mold coating formation method is provided for manufacturing a molded product coated with a coating layer having a uniform quality in its outside appearance. By continuously and unifyingly managing a mold opening amount and a mold closing force, an in-mold coating formation method and an in-mold coating formation apparatus are provided which are so formed that, if the control of a mold closing force and the control of a mold opening amount are continuously changed and at the same time a high precision and a high response are maintained, it is possible to enlarge a selectable range for selecting a molding condition, thereby producing an integrally formed molded product having an excellent outside appearance and whose coating layer has a high adhesion strength.
    Type: Application
    Filed: November 17, 2005
    Publication date: April 13, 2006
    Applicants: DAI NIPPON TORYO CO., LTD, UBE MACHINERY CORPORATION LTD.
    Inventors: Kenji Yonemochi, Yoshiaki Yamamoto, Kenji Oota, Toshio Arai, Etsuo Okahara, Kazuaki Kobayashi
  • Publication number: 20060043413
    Abstract: A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N?-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.
    Type: Application
    Filed: August 29, 2005
    Publication date: March 2, 2006
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yoshihiro Yamaguchi, Kenji Oota
  • Publication number: 20060038253
    Abstract: A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N?-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.
    Type: Application
    Filed: August 29, 2005
    Publication date: February 23, 2006
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Yoshihiro Yamaguchi, Kenji Oota
  • Publication number: 20060027910
    Abstract: A gate electrode (1a) is formed on the outer peripheral step portion (1?) of a semiconductor substrate (1) so as to face a pressure-contact supporting block (6), and a convex contacting portion (1g) is formed on a predetermined position on the surface of the gate electrode to contact the pressure contact supporting block. The surface area of the gate electrode ranging from the inner periphery to a position adjacent to the convex contacting portion, is coated with an insulation film (1d). The convex contacting portion (1g) is formed of a convex portion integral with the gate electrode or formed of another gate electrode (1a?).
    Type: Application
    Filed: October 4, 2005
    Publication date: February 9, 2006
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventors: Kenji Oota, Futoshi Tokunoh