Patents by Inventor Kenji Otobe

Kenji Otobe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9325153
    Abstract: An optical module capable of monitoring an inner temperature thereof by a simple arrangement is disclosed. The optical module installs an avalanche photodiode (APD). The APD generates the first photocurrent under a bias where the APD shows the multiplication factor thereof M equal to the unity, and the second photocurrent under another bias where the multiplication factor becomes greater than the unity. The operating temperature of the laser diode (LD) may be estimated from a ratio of the first photocurrent to the second photocurrent.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: April 26, 2016
    Assignee: Sumitomo Electric Device Innovations, Inc.
    Inventors: Kenji Otobe, Kenichi Nakayama
  • Publication number: 20150055946
    Abstract: An optical module capable of monitoring an inner temperature thereof by a simple arrangement is disclosed. The optical module installs an avalanche photodiode (APD). The APD generates the first photocurrent under a bias where the APD shows the multiplication factor thereof M equal to the unity, and the second photocurrent under another bias where the multiplication factor becomes greater than the unity. The operating temperature of the laser diode (LD) may be estimated from a ratio of the first photocurrent to the second photocurrent.
    Type: Application
    Filed: August 21, 2014
    Publication date: February 26, 2015
    Inventors: Kenji Otobe, Kenichi Nakayama
  • Publication number: 20020000570
    Abstract: The present invention relates to a power field-effect transistor capable of reducing third-order distortions. The power field-effect transistor 10a comprises a pulse-doped layer 16; a control electrode 18; a cap layer 20; ohmic electrodes 24a, 24b; heavily-doped semiconductor regions 22a, 22b; and a doped semiconductor region 26. The cap layer 20 is made of III-V compound semiconductor provided between the pulse-doped layer 16 and the control electrode 18. The heavily-doped semiconductor region 22a electrically connects the electrode 24a and the pulse-doped layer 16 to each other. The heavily-doped semiconductor region 22b electrically connects the electrode 24b and the pulse-doped layer 16 to each other. The doped semiconductor region 16 is provided in the cap layer 20 so as to electrically connect the heavily-doped semiconductor region 22a and the pulse-doped layer 16 to each other.
    Type: Application
    Filed: March 19, 2001
    Publication date: January 3, 2002
    Inventors: Shigeru Nakajima, Kenji Otobe, Ken Nakata
  • Patent number: 5835352
    Abstract: A power amplifying module has a package formed by welding a package bottom plate being a package substrate of a generally flat plate shape with a cap being a metal package cap of a generally rectangular box shape. A wiring substrate of a generally flat plate shape is placed on the package bottom plate and this wiring substrate is covered by the cap. There are two through holes formed in the wiring substrate and two heat spreaders of a generally flat plate shape are positioned in portions exposed through the through holes on the package bottom plate. Semiconductor devices sealed with a resin or the like are set by soldering or the like on respective surfaces of these heat spreaders.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: November 10, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ken-ichiro Matsuzaki, Gaku Ishii, Kenji Otobe, Tatsuya Hashinaga
  • Patent number: 5757251
    Abstract: In an electronic component, an electronic circuit board having an electronic element mounted on the major surface is mounted on a metal frame. The electronic circuit board is covered with a metal lid fitted on the metal frame and contained in a metal package constituted by the metal frame and the metal lid. At least at one notched portion is formed at least at one end of the electronic circuit board. A positioning projection formed on the metal frame engages with the notched portion. The mechanical precision and electrical characteristics are improved, so that an electronic component particularly excellent in high-frequency characteristics, which can be manufactured in simple manufacturing process, can be obtained.
    Type: Grant
    Filed: May 30, 1996
    Date of Patent: May 26, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tatsuya Hashinaga, Gaku Ishii, Kenji Otobe, Ken-ichiro Matsuzaki
  • Patent number: 5754402
    Abstract: A power amplifying module has at least one heat spreader mounted on a package substrate and exposed through a through hole provided in a wiring substrate, and at least one semiconductor chip forming a power amplifying circuit is mounted in a bare chip state on a surface of the at least one heat spreader as electrically connected to an electronic circuit pattern on the wiring substrate. Each of the package substrate and at least one heat spreader is made of a material having a thermal conductivity larger than that of a material making the wiring substrate. The module thus formed can emit the heat generated by the power amplifying module to the outside at high efficiency, thus achieving the power amplifying module with high performance and high reliability.
    Type: Grant
    Filed: June 21, 1996
    Date of Patent: May 19, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ken-ichiro Matsuzaki, Gaku Ishii, Kenji Otobe, Tatsuya Hashinaga
  • Patent number: 5493136
    Abstract: This invention provides a high-speed FET with a sufficiently high output current, and an FET having a high mobility of channel electrons and a high electron saturation rate. For this purpose, in this invention, a buffer layer, a first channel layer, a first spacer layer, a second channel layer, a second spacer layer, a third channel layer, and a capping layer are sequentially epitaxially grown on a semi-insulating GaAs semiconductor substrate. Drain and source regions are formed, and a gate electrode is formed to Schottky-contact the capping layer. Drain and source electrodes are formed to ohmic-contact the drain and source regions. Extension of a surface depletion layer from the substrate surface to a deep portion is prevented by the third channel layer closest to the substrate surface. For this reason, a sufficient quantity of electrons for forming a current channel are assured by the second and first channel layers.
    Type: Grant
    Filed: February 17, 1994
    Date of Patent: February 20, 1996
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Ken-ichiro Matsuzaki, Shigeru Nakajima, Nobuhiro Kuwata, Kenji Otobe, Nobuo Shiga, Ken-ichi Yoshida
  • Patent number: 5425167
    Abstract: A passive transformer which can be formed in an MMIC having a plurality of first-layer wirings formed on a substrate so that each of the first-layer wirings intersects a desired virtual line on the substrate; an insulating film for covering a substrate surface on which the first-layer wirings are formed; and a plurality of second-layer wirings formed on the insulating film so that each of the second-layer wirings intersects the virtual line and has opposite ends respectively connected to different ends of the first-layer wirings through contact holes. An inductor element having a spiral structure along the virtual line constitutes the first-layer wirings the contact holes and the second-layer wirings. The opposite ends of the inductor element are primary electrodes, and one end and a desired intermediate point of the inductor element are secondary electrodes. Because the transformer has such a structure, a three-dimensional coil can be formed on the substrate so that the transformer can be formed in an MMIC.
    Type: Grant
    Filed: August 29, 1994
    Date of Patent: June 20, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Nobuo Shiga, Kenji Otobe
  • Patent number: 5245505
    Abstract: A capacitance element for use in a high frequency signal processing circuit including a first-layer conductor formed on a substrate, a plurality of rod-like conductors arranged upright on the first-layer conductor, an inter-layer insulating film formed so as to cover the surfaces of the first-layer conductor and the rod-like conductors, and a second-layer conductor formed on the inter-layer insulating film at a position where the second-layer conductor superimposes on the first-layer conductor and the rod-like conductors. The opposite area of the electrodes increases by the areas of the side surfaces of the rod-like conductors so that it is possible to expect an increase of the capacity per unit area.
    Type: Grant
    Filed: April 10, 1992
    Date of Patent: September 14, 1993
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Nobuo Shiga, Kenji Otobe