Patents by Inventor Kenji Saitoh

Kenji Saitoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5946593
    Abstract: A semiconductor device is manufactured in accordance with the procedure as follows. At first, there is formed an interlayer insulating film including a SOG film (3) overlying a first metal wiring (1), a thin silicon nitride film (10) overlying the SOG film (3) and an oxide film (4) overlying the silicon nitride film (10). Next, an isotropic etching is performed to the oxide film (4). Then, there is formed a throughhole (7) through the interlayer insulating film so as to expose the first metal wiring (1) outward. Moreover, there is formed another oxide film (11) onto the semiconductor device on a way of a manufacturing process thereof. Thus, there is performed a whole anisotropic etching onto the other oxide film (11) by means of a dry etching process thus to reserve the other oxide film (11a) only on a side wall of the throughhole (7). Finally, there is formed a second metal wiring (8) connected to the first metal wiring (1) through the throughhole (7).
    Type: Grant
    Filed: February 20, 1996
    Date of Patent: August 31, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Kenji Saitoh
  • Patent number: 5891773
    Abstract: The invention provides a non-volatile semiconductor storage apparatus wherein silicon pillars are formed by epitaxial growth thereby to suppress a dispersion in channel length and improve the quality of a gate oxide film. In production, epitaxial silicon pillars are formed by selective epitaxial growth on a p-type silicon substrate, and a gate oxide film is formed over the overall area. Polycrystalline silicon is deposited and etched back to form a first polycrystalline silicon film serving as floating gates. Ion implantation is performed to form drain regions at the tops of the epitaxial silicon pillars and form a source region on the surface of the silicon substrate. A layered insulation film is formed, and polycrystalline silicon is deposited and etched back to form a second polycrystalline silicon film which covers over the side faces of the floating gates and serves as control gates. Bit lines are formed on the drain regions.
    Type: Grant
    Filed: July 23, 1997
    Date of Patent: April 6, 1999
    Assignee: NEC Corporation
    Inventor: Kenji Saitoh
  • Patent number: 5846861
    Abstract: In a method of manufacturing non-volatile semi-conductor memory including a memory cell transistor and a peripheral transistor, a floating gate and a control gate of the memory cell transistor is formed on a semiconductor substrate and a gate electrode of the peripheral transistor is formed on the semiconductor substrate. The control gate and gate electrode are covered with first and second insulating layers, respectively. A conductive layer is deposited to cover the first and second insulating layers. The conductive layer is etched back until the first and second insulating layers are exposed. An erasing gate of the memory cell transistor is formed by leaving the conductive layer on the insulating layer. A first mask layer on the second insulating layer and a second mask layer on the erasing gate is formed. The conductive layer remaining in the regions outside the masks is removed.
    Type: Grant
    Filed: October 30, 1996
    Date of Patent: December 8, 1998
    Assignee: NEC Corporation
    Inventor: Kenji Saitoh
  • Patent number: 5825690
    Abstract: A semiconductor non-volatile storage device has a memory cell array including a plurality of memory cells arranged in a form of matrix. Each of the memory cells has a charge accumulation layer and a control gate stacked on a semiconductor substrate for enabling electrical updating by increasing and decreasing of charge in the charge accumulation layer. An equal level of verification potential is applied for all of bit lines of the memory cells and a predetermined verification potential is applied to a selected control gate for performing re-writing for insufficiently written memory cells without generating data for re-writing per every verification by a logic circuit.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: October 20, 1998
    Assignee: NEC Corporation
    Inventor: Kenji Saitoh
  • Patent number: 5822389
    Abstract: A synchrotron exposure includes a synchrotron radiation source for generating a synchrotron radiation beam, and exposure unit having a mask stage for holding a mask and a wafer stage for holding a waver, a beam port for directing the radiation beam to the exposure unit, a mirror unit having a mirror for reflecting the radiation beam, a pre-alignment system for aligning the wafer relative to the wafer stage, a fine-alignment system for aligning the wafer held by the wafer stage relative to the mask held by the mask stage, a mask storage apparatus for storing the mask, a wafer storage apparatus for storing the wafer, a mask conveying apparatus for conveying the mask between the mask storage apparatus and the mask stage and a wafer conveying apparatus for conveying a wafer between the wafer storage apparatus and the wafer stage.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: October 13, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunichi Uzawa, Takao Kariya, Makoto Higomura, Nobutoshi Mizusawa, Ryuichi Ebinuma, Kohji Uda, Kunitaka Ozawa, Mitsuaki Amemiya, Eiji Sakamoto, Naoto Abe, Kenji Saitoh
  • Patent number: 5751426
    Abstract: A device and method for measuring the positional deviation between a plurality of diffraction gratings formed on the same object include an illumination optical system for illuminating the plurality of diffraction gratings with a light beam, the illumination by the optical system generating a plurality of diffracted light beams from the plurality of diffraction gratings, an interference optical system for forming at least one interference light beam from the plurality of diffracted light beams, a detector for detecting the at least one interference light beam, the result of the detection serving as the basis for measuring the positional deviation between the plurality of diffraction gratings, and a measuring portion for measuring the relative positional relation between the illumination optical system and the plurality of diffraction gratings.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: May 12, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Noriyuki Nose, Minoru Yoshii, Kenji Saitoh, Hiroshi Osawa, Koichi Sentoku, Toshihiko Tsuji, Takahiro Matsumoto
  • Patent number: 5721721
    Abstract: An encoder includes an electrically conductive reference scale having surface steps formed at predetermined positions; an electrically conductive probe having a tip disposed opposed to the reference scale; wherein the reference scale and the probe are relatively movable in a direction different from the opposing direction of the tip of the probe and the reference scale; a portion for applying an electrical voltage to between the reference scale and the probe; a portion for detecting a change in a tunnel current between the reference scale and the probe, to between which the electric voltage is applied by the voltage applying portion at the time of the relative movement between the scale and the probe, the detecting portion detecting the change in the tunnel current when the probe passes a position opposed to a surface step of the reference scale; and portion for detecting the amount of the relative movement between the scale and probe, on the basis of the detection by the change detecting portion.
    Type: Grant
    Filed: January 22, 1996
    Date of Patent: February 24, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshihiro Yanagisawa, Yuko Morikawa, Hiroshi Matsuda, Haruki Kawada, Kunihiro Sakai, Hisaaki Kawade, Ken Eguchi, Eigo Kawakami, Toshimitsu Kawase, Minoru Yoshii, Kenji Saitoh, Akihiko Yamano, Hiroyasu Nose
  • Patent number: 5717492
    Abstract: A position detection apparatus and method detects the relative positional relationship between first and second objects facing each other in a facing direction. First, second and third marks each serving as a physical optical element are provided on the first object, while a fourth mark serving as a physical optical element is provided on the second object. A light projector projects light onto the first and second objects A light detector detects a first light beam diffracted by the first mark and reflected by the second object, a second light beam diffracted by the second mark and reflected by the second object, and a third light beam diffracted by the third and fourth marks. A first position detector detects the relative positional relationship between the first and second objects in the facing direction based on signals representing the first and second light beams from the light detector.
    Type: Grant
    Filed: January 27, 1997
    Date of Patent: February 10, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koichi Sentoku, Kenji Saitoh, Hiroshi Osawa, Masanobu Hasegawa
  • Patent number: 5682239
    Abstract: Apparatus for detecting a positional deviation of two diffraction gratings of each of first and second pairs of diffraction gratings formed on a substrate, by utilizing an optical heterodyne interference method.
    Type: Grant
    Filed: September 15, 1995
    Date of Patent: October 28, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takahiro Matsumoto, Kenji Saitoh, Koichi Sentoku
  • Patent number: 5670809
    Abstract: A flash memory has diffused layers extending in a column direction to form channel regions between each two of the diffused layers, field oxide films extending in a row direction to divide the channel regions into separate channels arranged in a matrix, a floating gate disposed for each channel as a split gate, and a strip control gates extending in the row direction and overlying each row of the split floating gate. Each of the floating gates has a lower layer having a lower impurity concentration and an upper layer having a higher impurity concentration. The lower impurity concentration of the lower layer prevents fluctuations in device characteristics while the higher concentration of the upper layer enhances etch rates in two etching process for forming the floating gates of a matrix.
    Type: Grant
    Filed: March 21, 1996
    Date of Patent: September 23, 1997
    Assignee: NEC Corporation
    Inventor: Kenji Saitoh
  • Patent number: 5625453
    Abstract: A deviation detecting system for detecting a relative positional deviation between first and second diffraction gratings, includes a light source, an illuminating device for projecting first and second light beams from the light source, having different directions of polarization, onto the first and second diffraction gratings along different directions, a first signal detecting device for detecting a first interference light signal from the first diffraction grating, being based on a combination of diffraction light of the first light beam and diffraction light of the second light beam, a second signal detecting device for detecting a second interference light signal from the second diffraction grating, being based on a combination of diffraction light of the first light beam and diffraction light of the second light, a first phase difference detecting device for detecting a phase difference between the first and second interference light signals and, a second phase difference detecting device for producing
    Type: Grant
    Filed: October 26, 1994
    Date of Patent: April 29, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takahiro Matsumoto, Yoshiaki Ohtsu, Kenji Saitoh, Koichi Sentoku
  • Patent number: 5610718
    Abstract: A method and device for measuring the relative displacement between first and second diffraction gratings includes an interference optical system forming first and second interference rays of light from light diffracted from the first and second diffraction gratings and separating the first and second interference rays of light on the basis of the difference in their direction of polarization, a first detector for detecting the first interference ray of light to generate a first detection signal, a second detector for detecting the second interference ray of light to generate a second detection signal, and signal processing section for detecting the phase difference between the first and second detection signals and for determining the relative displacement between the first and second diffraction gratings on the basis of the phase difference.
    Type: Grant
    Filed: August 29, 1994
    Date of Patent: March 11, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventors: Koichi Sentoku, Takahiro Matsumoto, Noriyuki Nose, Minoru Yoshii, Kenji Saitoh
  • Patent number: 5585923
    Abstract: A method and apparatus for measuring the relative positional deviation between first and second diffraction gratings formed on an object includes determining the relative positional deviation of the first and second diffraction gratings while detecting and correcting an error produced in relation to detection of the positional deviation of the first and second diffraction gratings.
    Type: Grant
    Filed: September 28, 1994
    Date of Patent: December 17, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Noriyuki Nose, Takeshi Miyachi, Kenji Saitoh, Koichi Sentoku, Takahiro Matsumoto
  • Patent number: 5550635
    Abstract: A deviation detecting system for detecting a rotational deviation of an object, includes a pattern formed on the object and having a periodicity, a light source for providing light, a detecting device for projecting the light from the light source onto the pattern and for detecting at least two diffraction lights from the pattern with a predetermined detection plane, and a determining device for determining a rotational deviation of the object with respect to a predetermined axis, on the basis of the positions of incidence of the diffraction lights upon the detection plane as detected through the detection by the detecting device.
    Type: Grant
    Filed: October 28, 1994
    Date of Patent: August 27, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kenji Saitoh, Koichi Sentoku, Takahiro Matsumoto
  • Patent number: 5523976
    Abstract: A plurality of semiconductor memory cells are arranged in the form of a matrix and capable of electrically erasing and re-programming. Each of word lines is provided commonly to the memory cells in each row of the matrix and commonly connected to the gates of these memory cells, and each of bit lines is provided commonly to the memory cells in each column of the matrix and commonly connected to the drains of these memory cells. Each of common source lines is commonly connected to the sources of the memory cells in each pair of adjacent rows of the matrix. A memory cell group in a predetermined row or row pair of the matrix is operative as a redundant memory cell group for replacement of the other group.
    Type: Grant
    Filed: February 14, 1995
    Date of Patent: June 4, 1996
    Assignee: NEC Corporation
    Inventors: Takeshi Okazawa, Kenji Saitoh
  • Patent number: 5524131
    Abstract: A semiconductor device manufacturing SOR X-ray exposure apparatus wherein, after a mask and a semiconductor wafer are aligned, and SOR X-ray is used to transfer a semiconductor device pattern on the mask onto a resist on the semiconductor wafer. The apparatus includes a mirror unit and an exposure unit for exposing the wafer through the mask to the X-ray from the mirror unit. The mirror unit includes an X-ray mirror for diverging the X-ray in a desired direction, a first chamber for providing a desired vacuum ambience around the X-ray mirror and a first supporting device for supplying the X-ray mirror. The exposure unit includes a shutter for controlling the exposure, a mask stage for holding the mask, a wafer stage for holding the wafer, a second chamber for providing a desired He ambience around the mask stage and the wafer stage, a frame structure for mounting the mask stage and the wafer stage and a second supporting device for supporting the frame structure.
    Type: Grant
    Filed: May 15, 1995
    Date of Patent: June 4, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shunichi Uzawa, Takao Kariya, Makoto Higomura, Nobutoshi Mizusawa, Ryuichi Ebinuma, Kohji Uda, Kunitaka Ozawa, Mitsuaki Amemiya, Eiji Sakamoto, Naoto Abe, Kenji Saitoh
  • Patent number: 5519686
    Abstract: An encoder includes an electrically conductive reference scale having surface steps formed at predetermined positions; an electrically conductive probe having a tip disposed opposed to the reference scale; wherein the reference scale and the probe are relatively movable in a direction different from the opposing direction of the tip of the probe and the reference scale; a portion for applying an electrical voltage to between the reference scale and the probe; a portion for detecting a change in a tunnel current between the reference scale and the probe, to between which the electric voltage is applied by the voltage applying portion at the time of the relative movement between the scale and the probe, the detecting portion detecting the change in the tunnel current when the probe passes a position opposed to a surface step of the reference scale; and portion for detecting the amount of the relative movement between the scale and probe, on the basis of the detection by the change detecting portion.
    Type: Grant
    Filed: May 8, 1995
    Date of Patent: May 21, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Yoshihiro Yanagisawa, Yuko Morikawa, Hiroshi Matsuda, Haruki Kawada, Kunihiro Sakai, Hisaaki Kawade, Ken Eguchi, Eigo Kawakami, Toshimitsu Kawasa, Minoru Yoshii, Kenji Saitoh, Akihiko Yamano, Hiroyasu Nose
  • Patent number: 5502669
    Abstract: An electrically erasable and programmable memory device has a twin well electrically separated by an insulating wall into a plurality of sections respectively assigned to a plurality of memory sectors. The plurality of sections are selectively biased for erasing data bits stored in floating type field effect transistors that form the plurality of memory sectors.
    Type: Grant
    Filed: December 2, 1994
    Date of Patent: March 26, 1996
    Assignee: NEC Corporation
    Inventor: Kenji Saitoh
  • Patent number: 5483343
    Abstract: A wavelength compensator includes a reference vacuum tube having closed ends, wherein a laser beam enters the reference vacuum tube from one of the ends thereof and is reflected by the other end backwardly, an interference device for causing interference of the laser beam to produce an interference beam, and a light receiving device for receiving the interference beam which bears information related to a change in wavelength of the laser beam. The wavelength compensator further includes a specific arrangement which is effective to reduce vacuum deterioration of the reference vacuum tube.
    Type: Grant
    Filed: June 30, 1994
    Date of Patent: January 9, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Kazunori Iwamoto, Kenji Saitoh, Hiroshi Osawa
  • Patent number: 5481363
    Abstract: A method of detecting a relative positional deviation of a first object having a first grating mark with an optical power and a second object having a second grating mark with an optical power, is disclosed, wherein a projected radiation beam is diffracted by the first and second grating marks in sequence and, on the basis of a position of convergence on a light receiving surface of plural diffraction beams produced by the diffraction through the first and second grating marks and including a signal beam having been diffracted at a predetermined order by each of the first and second grating marks, the relative positional deviation is determined, a detection zone is defined on the light receiving surface, the signal beam is converged upon the detection zone, and a predetermined diffraction beam of the plural diffraction beams which, for a relative positional deviation of the first and second objects, shows displacement different from that of the signal beam is substantially prevented from being converged upon
    Type: Grant
    Filed: May 13, 1994
    Date of Patent: January 2, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masakazu Matsugu, Kenji Saitoh, Jun Hattori, Sakae Houryu