Patents by Inventor Kenji Shiratori

Kenji Shiratori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • MIS type semiconductor device and method for manufacturing same
    Patent number: 5877531
    Abstract: A P-type impurity is doped by oblique ion implantation into N-type impurity diffusion layers formed respectively on both sides of a gate electrode of a Pch MOS transistor, thereby canceling the impurity of at least a portion of an N-type region overlapped by the gate electrode, to thereby suppress a rise in the threshold voltage of the P-channel type MIS transistor due to the N-type impurity diffusion layer and suppress fluctuations in the amount of current that can be made to flow and the current-driving capacity.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: March 2, 1999
    Assignee: Nippondenso Co., Ltd.
    Inventors: Shigemitsu Fukatsu, Ryoichi Kubokoya, Kenji Shiratori, Nobuyuki Ooya
  • MIS type semiconductor device and method for manufacturing same
    Patent number: 5834347
    Abstract: A P-type impurity is doped by oblique ion implantation into N-type impurity diffusion layers formed respectively on both sides of a gate electrode of a Pch MOS transistor, thereby canceling the impurity of at least a portion of an N-type region overlapped by the gate electrode, to thereby suppress a rise in the threshold voltage of the P-channel type MIS transistor due to the N-type impurity diffusion layer and suppress fluctuations in the amount of current that can be made to flow and the current-driving capacity.
    Type: Grant
    Filed: October 30, 1997
    Date of Patent: November 10, 1998
    Assignee: Nippondenso Co., Ltd.
    Inventors: Shigemitsu Fukatsu, Ryoichi Kubokoya, Kenji Shiratori, Nobuyuki Ooya