Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.

Abstract: A semiconductor integrated circuit device includes a functional circuit part that includes a plurality of field effect transistors, a mode control circuit that receives a first control signal and that generates a second control signal that is used to change a logic state of the functional circuit part, an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal, and a control circuit that receives the second control signal and that generates a third control signal to the output control circuit. During a time period when the functional circuit part changes a logic state according to the second control signal, the output control circuit inverts the output signal of the functional circuit part according to the third control signal.

Abstract: A semiconductor integrated circuit device includes a functional circuit part that includes a plurality of field effect transistors, a mode control circuit that receives a first control signal and that generates a second control signal that is used to change a logic state of the functional circuit part, an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal, and a control circuit that receives the second control signal and that generates a third control signal to the output control circuit. During a time period when the functional circuit part changes a logic state according to the second control signal, the output control circuit inverts the output signal of the functional circuit part according to the third control signal.

Abstract: A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a mode information storage unit that stores first and second mode information, the first and second mode information being able to be set through the first bus-interface circuit, a first memory core that operates based on the first mode information, the first memory core being connected to the first bus-interface circuit and supplied with a first clock signal, a second memory core, the second memory core being supplied with a second clock signal and a select circuit that selectively connects the second memory core to the first or second bus-interface circuit based on predetermined switching information, in which the second memory core operates based on the second mode information when the second memory core is connected to the second bus-interface circuit.

Abstract: A semiconductor integrated circuit device includes a functional circuit part that includes a plurality of field effect transistors, a mode control circuit that receives a first control signal and that generates a second control signal that is used to change a logic state of the functional circuit part, an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal, and a control circuit that receives the second control signal and that generates a third control signal to the output control circuit. During a time period when the functional circuit part changes a logic state according to the second control. signal, the output control circuit inverts the output signal of the functional circuit part according to the third control signal.

Abstract: Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal.

Abstract: A semiconductor integrated circuit has K (K is a natural number of 2 or more) number of memory cells coupled to a same word line, and multiple sense amplifier circuits coupled to the memory cells. The multiple sense amplifier circuits are divided into N (N is a natural number of 2 or more) number of groups. Among the N number of groups, after a first group of sense amplifier circuits is activated and carrying out a predetermined read-out operation, a second group of the sense amplifier circuits is activated and the predetermined read-out operation is carried out, and an Nth group of the sense amplifier circuits is activated sequentially to carry out the predetermined read-out operation.

Abstract: Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal.

Abstract: The semiconductor integrated circuit device includes a voltage control circuit that generates a control voltage for deactivating a field effect transistor by a gate voltage. The voltage control circuit controls a voltage so as to substantially minimize the leakage current which flows when the field effect transistor is inactive with respect to a device temperature.

Abstract: A semiconductor integrated circuit according to an exemplary embodiment of the present invention includes a plurality of memory cells connected to one word line; a plurality of sense amplifier circuits that are connected to the memory cells and divided into an N number of groups; and N number of data inversion processing circuits that respectively receive data read out from the N number of groups of sense amplifier circuits, in which after a sense amplifier circuit of a first group terminates operation, a sense amplifier circuit of a second group different from the first group operates, and each of the data inversion processing circuits performs data inversion processing based on the data read out from each of the groups of sense amplifier circuits, and outputs the data to an output terminal of each of the data inversion processing circuits.

Abstract: A semiconductor integrated circuit has K (K is a natural number of 2 or more) number of memory cells coupled to a same word line, and multiple sense amplifier circuits coupled to the memory cells. The multiple sense amplifier circuits are divided into N (N is a natural number of 2 or more) number of groups. Among the N number of groups, after a first group of sense amplifier circuits is activated and carrying out a predetermined read-out operation, a second group of the sense amplifier circuits is activated and the predetermined read-out operation is carried out, and an Nth group of the sense amplifier circuits is activated sequentially to carry out the predetermined read-out operation.

Abstract: A semiconductor integrated circuit according to an exemplary embodiment of the present invention includes a plurality of memory cells connected to one word line; a plurality of sense amplifier circuits that are connected to the memory cells and divided into an N number of groups; and N number of data inversion processing circuits that respectively receive data read out from the N number of groups of sense amplifier circuits, in which after a sense amplifier circuit of a first group terminates operation, a sense amplifier circuit of a second group different from the first group operates, and each of the data inversion processing circuits performs data inversion processing based on the data read out from each of the groups of sense amplifier circuits, and outputs the data to an output terminal of each of the data inversion processing circuits.

Abstract: An integrated circuit apparatus according to one embodiment of the invention has an NMOS transistor and a source voltage controller which controls the source voltage of the NMOS transistor according to operation mode. The source voltage controller changes the source voltage according to temperature. Since this integrated circuit apparatus changes the source voltage of the MOSFET based on temperature, it is controlled to have desired leakage current regardless of temperature change.

Abstract: An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.

Abstract: The semiconductor integrated circuit device includes a voltage control circuit that generates a control voltage for deactivating a field effect transistor by a gate voltage. The voltage control circuit controls a voltage so as to substantially minimize the leakage current which flows when the field effect transistor is inactive with respect to a device temperature.

Abstract: An integrated circuit apparatus includes a SRAM cell array having a plurality of memory cells formed of CMOSFET arranged lattice-like. The SRAM cell array has a pair of power line and ground line in each of 1-bit sequences. The integrated circuit apparatus also includes a detector detecting the occurrence of latch-up for each 1-bit sequence and outputting a detection signal, and a power controller controlling a power supply voltage to the power line for each 1-bit sequence. The power controller reduces a voltage to be supplied to the power line in the 1-bit sequence where latch-up is occurring down to a predetermined value according to the detection signal.

Abstract: An integrated circuit apparatus according to one embodiment of the invention has an NMOS transistor and a source voltage controller which controls the source voltage of the NMOS transistor according to operation mode. The source voltage controller changes the source voltage according to temperature. Since this integrated circuit apparatus changes the source voltage of the MOSFET based on temperature, it is controlled to have desired leakage current regardless of temperature change.

Abstract: In one embodiment of the present invention, in a discrete MOSFET, the ZTC point is determined by combining the variation of the drain current induced by the variation of the threshold voltage in response to the temperature and the variation of the drain current induced by the variation of the mobility in response to the temperature. The chips configured with a number of circuits, however, include the circuits whose main operation regions of the MOSFETs are different. In CMOS circuits, the MOSFETs operate in the saturation region. On the other hand, in analog circuits, such as sense amplifiers or bandgap circuits, the MOSFETs operate in the linear region. In the design of the temperature dependence of the chip, the design is achieved by independently different models for respective MOSFETs whose operation regions are different.

Abstract: In a semiconductor integrated circuit device including a step-down circuit for stepping down an external power supply voltage to obtain an internal power supply voltage, the external power supply voltage can be applied to an internal signal processing circuit using a conventional terminal.

Abstract: A semiconductor memory device is fabricated from Bi-CMOS circuits and comprises a plurality of memory cells arranged in rows and columns, a plurality of word lines respectively coupled to the rows of the plurality of memory cells, a row address buffer unit coupled between first and second power voltage sources and supplied with row address bits for producing internal row address signals, a row address decoder unit responsive to the internal address signals and producing decode signals, a control signal buffer unit coupled between the first and second power voltage sources and supplied with an external control signal for producing a decode enable signal, and a word line driving unit responsive to the decode signals and selectively driving the word lines in the presence of the decode enable signal, wherein a monitoring unit is operative to monitor the power voltage level of one of the first and second power voltage sources and enables the control signal buffer unit to produce the decode enable signal when the p