Patents by Inventor Kenneth A. Lavallee

Kenneth A. Lavallee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9285417
    Abstract: System and method using low voltage current measurements to measure voltage network currents in an integrated circuit (IC). In one aspect, a low voltage current leakage test is applied voltage networks for the IC or microchip via one or more IC chip connectors. One or multiple specifications are developed based on chip's circuit delay wherein a chip is aborted or sorted into a lesser reliability sort depending whether the chip fails specification. Alternately, a low voltage current leakage test begins an integrated circuit test flow. Then there is run a high voltage stress, and a second low voltage current leakage test is thereafter added. Then, there is compared the second low voltage test to the first low V test, and if the measured current is less on second test, this is indicative of a defect present which may result in either a scrap or downgrade reliability of chip.
    Type: Grant
    Filed: January 2, 2013
    Date of Patent: March 15, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Daniel J. Poindexter, James M. Crafts, Karre M. Greene, Kenneth A. Lavallee, Keith C. Stevens
  • Publication number: 20140184262
    Abstract: System and method using low voltage current measurements to measure voltage network currents in an integrated circuit (IC). In one aspect, a low voltage current leakage test is applied voltage networks for the IC or microchip via one or more IC chip connectors. One or multiple specifications are developed based on chip's circuit delay wherein a chip is aborted or sorted into a lesser reliability sort depending whether the chip fails specification. Alternately, a low voltage current leakage test begins an integrated circuit test flow. Then there is run a high voltage stress, and a second low voltage current leakage test is thereafter added. Then, there is compared the second low voltage test to the first low V test, and if the measured current is less on second test, this is indicative of a defect present which may result in either a scrap or downgrade reliability of chip.
    Type: Application
    Filed: January 2, 2013
    Publication date: July 3, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Daniel J. Poindexter, James M. Crafts, Karre M. Greene, Kenneth A. Lavallee, Keith C. Stevens
  • Publication number: 20040066837
    Abstract: A method and apparatus for providing a more accurate reading of the junction temperature within an Integrated Circuit (IC) where temperature sensing elements are used that are sensitive to process changes. The apparatus stores an offset value in the IC that is used by internal temperature reading circuitry to adjust the temperature read/calculated from the sensing elements to more accurately reflect the actual junction temperature.
    Type: Application
    Filed: October 4, 2002
    Publication date: April 8, 2004
    Inventors: Joshua W. Armour, Craig Atherton, Zachary Berndlmaier, Jeffrey Durochia, Curt Guenther, Kenneth A. Lavallee, Gerard Salem
  • Patent number: 6557132
    Abstract: A method for determining common failure modes of an integrated circuit device under test is disclosed. In an exemplary embodiment of the invention, a test pattern is applied to a series of inputs of the device under test. A set of output data generated by the device under test is then compared to a set of expected data, with the set of output data being generated by the device under test in response to the test pattern. It is then determined whether the set of output data has passed the test, with the set of output data passing the test if the set of output data matches the set of expected data. If the set of output data has not passed the test, then it is determined whether an output signature corresponding to the set of output data matches a previously stored output signature. Fail data corresponding to the output signature is then stored if the output signature matches a previously stored output signature.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: April 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: David V. Gangl, Matthew Sean Grady, David John Iverson, Kenneth A. Lavallee, Robert Edward Shearer
  • Publication number: 20020116675
    Abstract: A method for determining common failure modes of an integrated circuit device under test is disclosed. In an exemplary embodiment of the invention, a test pattern is applied to a series of inputs of the device under test. A set of output data generated by the device under test is then compared to a set of expected data, with the set of output data being generated by the device under test in response to the test pattern. It is then determined whether the set of output data has passed the test, with the set of output data passing the test if the set of output data matches the set of expected data. If the set of output data has not passed the test, then it is determined whether an output signature corresponding to the set of output data matches a previously stored output signature. Fail data corresponding to the output signature is then stored if the output signature matches a previously stored output signature.
    Type: Application
    Filed: February 22, 2001
    Publication date: August 22, 2002
    Applicant: International Business Machines Corporation
    Inventors: David V. Gangl, Matthew Sean Grady, David John Iverson, Kenneth A. Lavallee, Robert Edward Shearer