Abstract: A computerized router is provided with local protection regions in which the orientation of conductors in a given conductor layer is restricted to a particular orientation without affecting the allowable orientations of conductors in that layer in other portions of the routing area. Such local protection regions may apply to one or more signal conductor layers. This capability may be provided for a router which does not have it by the addition of artificial features to the components to be connected by the router. These features may be obstructions or conductors to be used in routing signal paths. Obstructions are sized and positioned to restrict conductors in the local protection regions to the desired orientation.

Abstract: A packaged electronics system, having respective portions each with respective input and output ports, and having interconnection busses between certain of these ports, is tested as follows. Each input port has a set of first transmission gates associated therewith for selectively disconnecting it during testing from the end of each interconnection bus connected bit during normal operation. Each input port has a second set of transmission gates associated therewith for selectively applying test vectors thereto during testing as provided in parallel form from a serially loaded shift register. Each output port connects to the input connections of a respective set of tristate drivers for selectively applying its output signals at relatively low source impedance to at least one interconnection bus connected from the output connections of that set of tristate drivers.

Abstract: An auxiliary monolithic integrated circuit chip provides both buffer amplification and testing interfaces. Off-the-shelf monolithic integrated circuit chips can be connected into an electronics system using one of these auxiliary buffer chips before each input port and after each output port, to implement functional testing similar to that done on monolithic integrated circuit chips with built-in test circuitry.

Abstract: Apparatus for measuring or compensating for phase or time delay between a reference signal and a desired signal produces an approximate error signal by differentially summing the desired and reference signals. The appoximate error signal is then used, in a feedback loop, to control application of an adaptive delay to each of the reference and desired signals. The total lead or lag difference is represented by the difference between the two delays applied to the reference and desired signals, respectively. The phase or time delay measurement or compensation arrangements may be applied to linear variable differential transformers, synchronous AM detectors, zero crossing detectors and phase locked loops. Variations on this basic technique can yield substantially exact measurement or compensation. The invention is applicable to sampling arrangements including oversampling/decimation or interpolation/decimation to increase compensation accuracy to any desired degree.

Abstract: Built-in test circuitry, which is appropriate for monolithic integrated circuit chips that are to be connected in a plural-chip package, uses electronic token passing to select one of the test input ports in the circuitry to be tested for application of test input vectors. The built-in test circuitry also uses electronic token passing to select one of the test output ports in the circuitry to be tested from which test results are to be supplied. Methods for testing based on these token passing procedures are described.

Abstract: Built-in test circuitry, which is appropriate for monolithic integrated circuit chips that are to be connected in a plural-chip package, uses electronic token passing to select one of the test input ports in the circuitry to be tested for application of test input vectors. The built-in test circuitry also uses electronic token passing to select one of the test output ports in the circuitry to be tested from which test results are to be supplied.

Abstract: A method and apparatus are provided for disposing a polymer film on an irregularly-shaped substrate at relatively high temperatures. In particular, the method and apparatus of the present invention provide a system for the packaging of very large scale integrated circuit chips. The system of the present invention particularly solves problems associated with high temperature processing and problems associated with the highly irregular surfaces that result. Nonetheless, the resultant product is capable of being fashioned into circuit chip systems which are independently testable and which may be reconfigured after testing by removal of the polymer film itself.

Abstract: A method and apparatus for improved digital processing of the analog echo signals in a coherent imaging system is described which simplifies the channel circuitry requirements. The analog echo signals detected with a phased array of transducer elements are first compressed in a non-linear manner then expanded non-linearly with analog-to-digital converter means to provide increased instantaneous dynamic range in the overall system. Representative phased array coherent imaging systems having the improved digital processing means are also disclosed.

Abstract: The discrete Fourier transform is continuously calculated at input signal sample rate using recursive filtering, rather than transversal filtering. This reduces the number of complex digital multiplications per computational cycle to N, the number of spectral components in the discrete Fourier transform, where rectangular truncation window or a new exponential window is used. Where a triangular truncation window is used the number of complex digital multiplications per computational cycle is reduced to 2N.

Abstract: The utilization of a removable overlay layer together with its associated metallization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuit systems to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips which are either temporarily or permanently affixed in an integrated circuit chip package.

Abstract: A method and apparatus are provided for disposing a polymer film on an irregularly-shaped substrate at relatively high temperatures. In particular, the method and apparatus of the present invention provide a system for the packaging of very large scale intergrated circuit chips. The system of the present invention particularly solves problems associated with high temperature processing and problems associated with the highly irregular surfaces that result. Nonetheless, the resultant product is capable of being fashioned into circuit chip systems which are independently testable and which may be reconfigured after testing by removal of the polymer film itself.

Abstract: The surface of a polymer dielectric layer is scanned repeatedly with a high energy continuous wave laser in a pattern to create via holes of desired size, shape and depth. This is followed by a short plasma etch. The via holes are produced at commercial production rates under direct computer control without use of masks and without damage to conductor material underlying the dielectric layer. A two-step technique usable to form a large hole to a partial depth in the dielectric layer and several smaller diameter holes within the large hole through the remainder of the dielectric layer depth allows formation of a large number of holes in a given area of a thick dielectric layer.

Abstract: The utilization of a removable overlay layer together with its associated metalization pattern, is used to effectively provide wafer scale integration for integrated circuit chips. The method and configuration of the present invention provide for the fabrication and testing of systems which are otherwise untestable. The present invention also permits integrated circuit systems to be tested in their final configuration in terms of speed and operating environment and the invention eliminates many of the problems associated with wafer or chip probes. The present invention also utilizes special test chips which are either temporarily or permanently affixed in an integrated circuit chip package.

Abstract: The present invention employs a high density interconnect method to take advantage of a packaging arrangement in which full customization of an integrated circuit chip package is providable in a single metallization layer. The integrated circuit chips are positioned to take full advantage of a wiring layer which includes a plurality of periodically interrupted conductor patterns. All of the customization is provided in a single layer which may be readily fabricated and produced in a single day making it possible for extremely rapid turn around time in the design of complex integrated circuit systems, particularly those constructed from readily available integrated circuit components including microprocessors, random access memory chips, decoders and the like. An integrated circuit is also disclosed for fully taking advantage of the capabilities of testing made available by the high density interconnect system.

Abstract: An adaptive method and system are disclosed for providing high density interconnections of very large scale integrated circuits on a substrate. The procedure is performed in four basic steps: first an artwork representation for the interconnections of the integrated circuits is generated. This artwork representation is stored in a computer data base and assumes the integrated circuits to be at predetermined ideal locations and positions on the substrate. Second, using imaging, the actual positions of each integrated circuit on the substrate are determined. The actual positions of the integrated circuits are compared with their ideal positions to compute an offset and rotation for each integrated circuit on the substrate. Third, the computed offsets and rotations are then used to modify the artwork representation stored in the data base to account for the actual locations and positions of the integrated circuits on the substrate.

Abstract: An ultrasonic imaging processing system includes transducers and means to generate in an analog fashion, in-phase and quadrature phase signals. These signals are converted to digital form and a butterfly phase rotator circuit is employed to correct for phase differences in beam steering and focusing. In particular, speed and simplicity is achieved through the utilization of read only memory means providing appropriate function values for phase correction in conjunction with digital multiplication and summing circuitry.

Abstract: Sampled and digitized in-phase and quadrature phase signals are algebraically accumulated in offset accumulators, the contents of which are periodically employed to adjust the value of offset correction factors added to each signal path. Additionally, the absolute values of the in-phase and quadrature phase signals are accumulated in gain accumulators, the contents of which are periodically employed to adjust the gain factor multiplier in one of the signal paths.

Abstract: A frame synchronizer having broad applicability in television systems is particularly adapted for use in a chrominance time-compressed, luminance bandwidth reduced television system. The frame synchronizer, which separates the composite video signal into its component parts and thereby minimizes the dynamic range required to digitize the signal, demodulates the chrominance signal into its quadrature components and separates the luminance signal. The synchronization signal in the composite video signal generates slave distribution signals and slave horizontal and vertical addresses. The separated chrominance quadrature components and the luminance signal are digitized and, along with the slave distribution signals and the slave horizontal and vertical addresses, are temporarily stored in first-in, first-out memories which provide independent buffering and thereby accommodate a high degree of mismatch between master and slave timing.

Abstract: A simple digital filter having only a single multiplier operates to extract the pilot tone from a demodulated and digitized FM stereo signal. The number of poles in the filter is chosen so that the filter output is also usable to produce a digitized representation of the carrier tone for the left minus right stereo channel. This signal is in turn used to decode the input representation into the desired left and right channel signals. The circuit of the present invention is particularly amenable to fabrication on an integrated circuit chip.

Abstract: A reconfigurable remote control transmitter is disclosed that has the ability to learn, store and repeat the remote control codes from any other infrared transmitter. The reconfigurable remote control transmitter includes an infrared receiver, a microprocessor, nonvolatile and scratch pad random access memories, and an infrared transmitter. The microprocessor application is divided into four main categories: learning, storing, retransmitting, and user interface. In the learning process, the reconfigurable remote control transmitter receives and decodes the transmissions from another remote control transmitter. The process is repeated at least twice for each key to make sure that it has been properly received and decoded. Once the data has been received and decoded, it is stored for later use. In order to do this, the received and decoded data is compressed so that it can fit into the nonvolatile memory.