Abstract: A method is presented for constructing fully-aligned top-via interconnects by employing a subtractive etch process. The method includes building a first metallization stack over a substrate, depositing a first lithography stack over the first metallization stack, etching the first lithography stack and the first metallization stack to form a receded first metallization stack, and depositing a first dielectric adjacent the receded first metallization stack. The method further includes building a second metallization stack over the first dielectric and the receded first metallization stack, depositing a second lithography stack over the second metallization stack, etching the second lithography stack and the second metallization stack to form a receded second metallization stack, and trimming the receded first metallization stack to form a via connecting the receded first metallization stack to the receded second metallization stack.

Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

Abstract: Integrated chips and methods of forming the same include forming upper dummy lines over lower conductive lines. The lower conductive lines are recessed to form conductive vias between the lower conductive lines and the upper dummy lines. The upper dummy lines are replaced with upper conductive lines that contact the conductive vias.

Abstract: A method is presented for constructing fully-aligned top-via interconnects by employing a subtractive etch process. The method includes building a first metallization stack over a substrate, depositing a first lithography stack over the first metallization stack, etching the first lithography stack and the first metallization stack to form a receded first metallization stack, and depositing a first dielectric adjacent the receded first metallization stack. The method further includes building a second metallization stack over the first dielectric and the receded first metallization stack, depositing a second lithography stack over the second metallization stack, etching the second lithography stack and the second metallization stack to form a receded second metallization stack, and trimming the receded first metallization stack to form a via connecting the receded first metallization stack to the receded second metallization stack.

Abstract: Integrated chips and methods of forming the same include forming a lower conductive line over an underlying layer. An upper conductive via is formed over the lower conducting lines. An encapsulating layer is formed on the lower conductive line and the upper conductive via using a treatment process that converts an outermost layer of the lower conductive line and the upper conductive via into the encapsulating layer.

Abstract: Integrated chips and methods of forming the same include forming upper dummy lines over lower conductive lines. The lower conductive lines are recessed to form conductive vias between the lower conductive lines and the upper dummy lines. The upper dummy lines are replaced with upper conductive lines that contact the conductive vias.

Abstract: Air-gap containing metal interconnects with selectively-deposited dielectric material are provided. In one aspect, a method of forming an interconnect structure with air-gaps includes: forming interconnect metal lines separated from a first dielectric by a liner and a barrier layer; depositing a capping layer and an inhibitor layer over the interconnect metal lines; patterning the capping layer, inhibitor layer and first dielectric to form the air-gaps between the interconnect metal lines; selectively depositing a second dielectric to form a bridge of the second dielectric over/pinching off the air-gaps, wherein the barrier layer inhibits deposition of the second dielectric along the sidewalls of the interconnect metal lines, and the inhibitor layer inhibits deposition of the second dielectric on top of the interconnect metal lines. An interconnect structure is also provided.

Abstract: Air-gap containing metal interconnects with selectively-deposited dielectric material are provided. In one aspect, a method of forming an interconnect structure with air-gaps includes: forming interconnect metal lines separated from a first dielectric by a liner and a barrier layer; depositing a capping layer and an inhibitor layer over the interconnect metal lines; patterning the capping layer, inhibitor layer and first dielectric to form the air-gaps between the interconnect metal lines; selectively depositing a second dielectric to form a bridge of the second dielectric over/pinching off the air-gaps, wherein the barrier layer inhibits deposition of the second dielectric along the sidewalls of the interconnect metal lines, and the inhibitor layer inhibits deposition of the second dielectric on top of the interconnect metal lines. An interconnect structure is also provided.