Abstract: A method and system for reverse link interference cancellation. One method comprises demodulating and decoding at least one signal sent from at least one access terminal and received by a first base station, sending demodulated, decoded information of the signal to a second base station, reconstructing the signal at the second base station, and subtracting the reconstructed signal from a buffer at the second base station.

Abstract: Techniques for generalized pilot interference cancellation in a communications receiver. In an exemplary embodiment, a residual pilot is cancelled from a post-traffic cancellation signal following initial first-pass pilot cancellation. Residual pilot cancellation is achieved by adding the first-pass cancelled pilot as earlier stored in memory back to the post-traffic cancellation signal, and pilot filtering the resulting signal to generate an improved pilot interference estimate. In an alternative exemplary embodiment, an arbitrary number of iterations may be applied to generate the pilot interference estimate by successively storing each generated pilot interference estimate in memory.

Abstract: A receiver unit includes a first buffer that receives and stores digitized samples at a particular sample rate and a data processor that retrieves segments of digitized samples from the first buffer and processes the retrieved segments with a particular set of parameter values. The data processor is operated based on a processing clock having a frequency that is (e.g., ten or more times) higher than the sample rate. Multiple instances of the received signal can be processed by retrieving and processing multiple segments of digitized samples from the first buffer. The receiver unit typically further includes a receiver that receives and processes a transmitted signal to provide the digitized samples and a controller that dispatches tasks for the data processor. The data processor can be designed to include a correlator, a symbol demodulation and combiner, a first accumulator, and a second buffer, or a combination thereof.

Abstract: The present invention is an improved method and circuit for reducing the amount of time a mobile receiver spends in the active phase of a slot in a communications system utilizing a slotted paging mechanism. The invention allows the awake time to be configured for the minimum interval needed to demodulate the paging channel messages of interest. The invention includes a means to adjust the timing reference of the fingers to compensate for a sleep duration not an integral multiple of the PN sequence period, and a means to adjust the deinterleaver frame reference timing to compensate for a sleep duration not an integral multiple of the frame interval, and a means to initialize the frequency tracking, gain scaling, and DC bias loops, if any, of the analog receiver chain to minimize the time needed to re-lock these loops.

Abstract: Coherent detection of high-speed digital wireless communications becomes more difficult when the frequencies of the transmitter and receiver oscillators do not coincide. A frequency-locked loop may be used to characterize this frequency offset by processing the samples received on a pilot channel. Rather than using the offset information thus derived to correct the frequency of the received signal, the invention realizes a considerable computational savings by applying a frequency correction to the despread pilot samples instead.

Abstract: A method and circuit for controlling a mobile station operating in a slotted paging environment. The circuit comprises a low power clock for generating a low frequency clock signal; a clock signal generator for generating a high frequency clock signal; a synchronization logic circuit for synchronizing the low frequency clock signal to the high frequency clock signal; a frequency error estimator for measuring an estimated low frequency clock error; and a sleep controller for removing power from the clock signal generator for the corrected sleep duration value, thereby conserving power between assigned paging slots. During the awake time, the low frequency clock signal is resynchronized to the high frequency clock, thereby correcting for any frequency error in the less accurate low power clock during sleep mode.

Abstract: An integrated search processor used in a modem for a spread spectrum communications system buffers receive samples and utilizes a time sliced transform processor operating on successive offsets from the buffer. The search processor autonomously steps through a search as configured by a microprocessor specified search parameter set, which can include the group of antennas to search over, the starting offset and width of the search window to search over, and the number of Walsh symbols to accumulate results at each offset. The search processor calculates the correlation energy at each offset, and presents a summary report of the best paths found in the search to use for demodulation element reassignment. This reduces the searching process related workload of the microprocessor and also reduces the modem costs by allowing a complete channel element modem circuit to be produced in a single IC.

Abstract: The finite impulse response (FIR) filter is implemented as a table using read-only memory (ROM). The FIR filter table stores a pre-calculated output filter value for each permissible combination of input values to be filtered. Streams of input values are successively shifted into the table and corresponding output values are successively output. In an exemplary implementation, the FIR filter is employed within a digital cellular telephone for use in smoothing a digital signal to be transmitted. The size of the required FIR filter table is minimized by exploiting constraints imposed upon the signal to be filtered and by exploiting linearity and symmetry within the filter itself. More specifically, the telephone employs a data burst randomizer to provide a data signal composed of sequences of null or 0 values and sequences of antipodal values (+1's and -1's).

Abstract: An integrated search processor used in a modem for a spread spectrum communications system buffers receive samples and utilizes a time sliced transform processor operating on successive offsets from the buffer. The search processor autonomously steps through a search as configured by a microprocessor specified search parameter set, which can include the group of antennas to search over, the starting offset and width of the search window to search over, and the number of Walsh symbols to accumulate results at each offset. The search processor calculates the correlation energy at each offset, and presents a summary report of the best paths found in the search to use for demodulation element reassignment. The search is done in a linear fashion independent of the probability that a signal being searched for was transmitted at any given time.

Abstract: The present invention involves demodulating a signal in a spread spectrum multiple access system employing a pilot on the forward link. The rake receiver separates the signal processing based on the period over which the processing occurs. Symbol rate processing is performed by a single time-shared multiply-accumulate datapath that services multiple finger front ends and a searcher front end. The front ends are dedicated circuits that perform all chip rate processing, producing a data vector and asserting a flag indicating the results are ready to be serviced by the shared datapath. A datapath controller arbitrates use of the datapath between the finger front ends, the searcher front end, and combining functions, configuring the datapath to service them on a first-come, first-serve basis. The controller sequences the datapath through a fixed routine as dictated by the signal processing associated with the block being serviced.

Abstract: A modulator for a spread spectrum telecommunication system not only receives local data and processes it, but also receives input data from one or more other modulators, sums the input data with the local data, and provides the sum as data for a subsequent modulator or as final output for a transmit power amplifier. The modulator includes an input block and an output block and, depending on a control data signal, input data will be summed with the internally generated local data of the modulator before being provided to the output block. The output data can include parity data. The parity data can be used to check for faults such as might be introduced, for example, by a faulty connection or broken hard-wired interconnect. If an error is detected, the summation function of the transmit modulator can be automatically disabled.

Abstract: An integrated search processor used in a modem for a spread spectrum communications system buffers receive samples and utilizes a time sliced transform processor operating on successive offsets from the buffer. The search processor autonomously steps through a search as configured by a microprocessor specified search parameter set, which can include the group of antennas to search over, the starting offset and width of the search window to search over, and the number of Walsh symbols to accumulate results at each offset. The search processor calculates the correlation energy at each offset, and presents a summary report of the best paths found in the search to use for demodulation element reassignment. The search is done in a linear fashion independent of the probability that a signal being searched for was transmitted at any given time.

Abstract: An integrated demodulation processor used in a modem for a spread spectrum communications system despreads multipath receive signals then uses a time sliced transform processor to process the multiple signals in to a single series of soft decision results. The demodulation processor uses a single transform engine which operates on a time slice basis. The output of the processor engine cascade through a pipeline processor which, on a time slice basis, operates on signals corresponding to each multipath receive signal. The processed results are dual maxima decoded to provide soft decision data.