Abstract: A method and apparatus for selectively providing hierarchy to a circuit design. The present invention contemplates providing a number of hierarchical statements in a description of a circuit design, wherein the syntax of the hierarchical statements allows the hierarchical statements to be visible when providing a first representation of the circuit design and effectively invisible when providing a second representation of the circuit design.

Abstract: The present invention relates to a method and apparatus for efficiently managing the I/O design of an integrated circuit. The present invention automatically selects and interconnects a number of I/O cells selected from a design library to form an I/O interface. A user interface is provided for receiving a number of parameters provided by the circuit designer. The parameters preferably provide specific information about a circuit design. A set of circuit design assembly rules are also provided, which define the available I/O cells and the appropriate interconnections of the available I/O cells. A computer program then selects and assembles the I/O cells in accordance with the user provided parameters and the set of circuit design assembly rules.

Abstract: A method and apparatus for incrementally optimizing a circuit design. The present invention provides an iterative EDA process that only requires the optimization, placement and routing of the actual changes made during a each design iteration, and leaves the remainder of the circuit design in a fixed state.

Abstract: A method and apparatus for using an optimization tool to optimize a design that uses a gated clock structure. In short, the present invention allows a standard optimizer tool to determine the relative timing of two or more signals that arrive at a logic gate, wherein the logic gate forms a gated clock signal. Typically, standard optimizer tools can only check the relative timing between two or more signals that arrive at a storage element. In accordance with the present invention, selected logic gates may be modeled as a storage element. Thus, a standard optimizer tool may be used to correctly optimize a design that uses a gated clock structure, and in particular, to correctly optimize the logic that provides the clock and enable signals to a clock gating element.

Abstract: A method and apparatus for providing optimization parameters to an EDA logic optimizing tool. The optimization parameters for selected circuit modules within a circuit design database may be stored such that a particular optimization parameter set can be uniquely identified by a search capability of a data processing system, thereby enabling the logic optimizer tool to select and access a particular optimization parameter set from a collection of optimization parameter sets. Further, the optimization parameters may be stored such that the corresponding optimization parameters can be collectively viewed by a circuit designer.

Abstract: A method and apparatus for optimizing a circuit design having multi-cycle paths therein. In an exemplary embodiment, a circuit design having a number of multi-cycle paths may be optimized by: identifying at least one of the number of multi-cycle paths within the circuit design, and identifying the corresponding qualified clocks associated therewith; replacing selected ones of the corresponding clocks with replacement clocks; and optimizing the circuit design using the replacement clocks. By using a replacement clock that has a clock period equal to the corresponding clock, which is typically a qualified clock, a standard optimization tool may correctly optimize the circuit design.

Abstract: A method and apparatus for monitoring the performance of a circuit optimization tool. The present invention contemplates inserting a number of performance monitoring commands into selected ones of a number of optimization scripts, wherein selected ones of the performance monitoring commands provide a number of performance related results when executed. Thereafter, the number of optimization scripts may be executed to optimize the circuit design. The number of results provided by the performance monitoring commands may then be assembled and analyzed by the circuit designer to identify any performance related problems.

Abstract: A method and apparatus for identifying gated clocks within a circuit design. In a typical design, each of the number of gated clock signals is uniquely determined by a particular logical combination of a number of raw clock signals and a number of enable signals. In the present invention, the gated clock signals may be identified by: identifying which of the number of raw clock signals is coupled, through combinational logic, to a selected one of the number of state devices, thereby resulting in an identified raw clock signal; identifying which of the number of enable signals is coupled, through combinational logic, to the selected one of the number of state devices, thereby resulting in an identified enable signal; and determining which of the number of gated clock signals is uniquely determined by the particular combination of the identified raw clock signal and the identified enable signal.