Abstract: Some embodiments of the invention include a thruster system comprising a thruster and a pulsing power supply. The thruster may include a gas inlet port; a plasma jet outlet; and a first electrode. In some embodiments, the pulsing power supply may provide an electrical potential to the first electrode with a pulse repetition frequency greater than 10 kHz, a voltage greater than 5 kilovolts. In some embodiments, the pressure downstream from the thruster can be less than 10 Torr. In some embodiments, when a plasma is produced within the thruster by energizing a gas flowing into the thruster through the gas inlet port, the plasma is expelled from the thruster through the plasma jet outlet.

Abstract: Some embodiments of the invention include a pre-pulse switching system. The pre-pulsing switching system may include: a power source configured to provide a voltage greater than 100 V; a pre-pulse switch coupled with the power source and configured to provide a pre-pulse having a pulse width of Tpp; and a main switch coupled with the power source and configured to provide a main pulse such that an output pulse comprises a single pulse with negligible ringing. The pre-pulse may be provided to a load by closing the pre-pulse switch while the main switch is open. The main pulse may be provided to the load by closing the main switch after a delay Tdelay after the pre-pulse switch has been opened.

Abstract: A low-power digital logic architecture exhibits the same logic and voltage level behavior as standard digital logic. A logic switch and a pair of unidirectional switches are used to control the direction of charge flow in a switched-inductor capacitor (SLC) circuit, allowing the inductor to pull charge back-and-forth from one side of the load capacitor to the other to both switch the logical state at the top of the capacitor and to recycle and store the charge in the capacitor itself.

Abstract: An asynchronous pipeline structure includes a plurality of functional blocks comprising dynamic logic, each block precharged to an idle state responsive to a precharge control signal applied thereto, with each block, upon being precharged, receiving input data thereto for processing, and holding output data generated thereby during an evaluate phase, independent of a reset of the input data; for each block, a completion detector circuit coupled to the output of the functional block, the completion detector circuit generating an acknowledgement signal that indicates validity or absence of data at the output of the block; and for each block, a precharge control circuit generating a precharge signal, wherein for a given block, a first input to the precharge control circuit comprises the acknowledgment signal from a downstream completion detector, and second input to the precharge control circuit comprises the precharge signal from an upstream precharge control circuit.

Abstract: A data flow controller for reconfigurable computers. The novel data flow controller includes a first circuit for selecting one of a plurality of operating conditions and a second circuit for determining if the selected condition is met and outputting a control signal accordingly. In an illustrative embodiment, the operating conditions include: when all enabled data available signals are asserted and all enabled space available signals are asserted; when any enabled data available signal is asserted and all enabled space available signals are asserted; when all enabled data available signals are asserted and any enabled space available signal is asserted; and when any enabled data available signal is asserted and any enabled space available signal is asserted. By allowing a configurable element to operate under different possible conditions, data flow signals can also then be used to control what operation the element performs, in addition to controlling when.

Abstract: A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.

Abstract: An asynchronous pipeline structure includes a plurality of functional blocks comprising dynamic logic, each block precharged to an idle state responsive to a precharge control signal applied thereto, with each block, upon being precharged, receiving input data thereto for processing, and holding output data generated thereby during an evaluate phase, independent of a reset of the input data; for each block, a completion detector circuit coupled to the output of the functional block, the completion detector circuit generating an acknowledgement signal that indicates validity or absence of data at the output of the block; and for each block, a precharge control circuit generating a precharge signal, wherein for a given block, a first input to the precharge control circuit comprises the acknowledgment signal from a downstream completion detector, and second input to the precharge control circuit comprises the precharge signal from an upstream precharge control circuit.

Abstract: A digital signal processing apparatus includes a digital circuit device having one or more elements configured to process digital data; a power supply configured to deliver a controllable operating voltage for the one or more elements; control logic configured to receive feedback signals from each of the one or more elements, the feedback signals indicative of a rate at which data is moving through each individual element; and the control logic configured to output a control signal to the power supply so as to cause the power supply to reduce the operating voltage for the one or more elements responsive to a decreasing workload detected therein, and to cause the power supply to increase the operating voltage for the one or more pipelines responsive to an increasing workload detected therein.

Abstract: Methods for tracking the relative velocity between a vehicle and a target that uses both a measured velocity as well as an estimate of the velocity that is based on tracking the peaks in a laser vibrometer return signal.

Abstract: Methods for tracking the relative velocity between a vehicle and a target that uses both a measured velocity as well as an estimate of the velocity that is based on tracking the peaks in a laser vibrometer return signal.

Abstract: A data flow controller for reconfigurable computers. The novel data flow controller includes a first circuit for selecting one of a plurality of operating conditions and a second circuit for determining if the selected condition is met and outputting a control signal accordingly. In an illustrative embodiment, the operating conditions include: when all enabled data available signals are asserted and all enabled space available signals are asserted; when any enabled data available signal is asserted and all enabled space available signals are asserted; when all enabled data available signals are asserted and any enabled space available signal is asserted; and when any enabled data available signal is asserted and any enabled space available signal is asserted. By allowing a configurable element to operate under different possible conditions, data flow signals can also then be used to control what operation the element performs, in addition to controlling when.

Abstract: A reconfigurable processor architecture. A reconfigurable processor is an array of a multiplicity of various functional elements, between which the interconnections may be programmably configured. The inventive processor is implemented on a single substrate as a network of clusters of elements. Each cluster includes a crossbar switching node to which a plurality of elements is connected via ports. Additional ports on the crossbar switching node connect to the switching nodes of nearest neighbor clusters. The crossbar switching nodes allow pathways to be programmably set between any of the ports, and any pathway may be set to be either registered or unregistered. The use of clusters of processing elements allows complete freedom of local connectivity for effective configuration of many different processing functions. Wide area interconnection is more restricted, but, since it is less used, does not significantly restrict configurability.

Abstract: A communication path includes N channels or information pathways, each of which is bidirectional, i.e. each channel may be set to either send or receive. The number of send channels (S) and receive channels (R) is programmably set, such that S+R=N. The total bandwidth is N*B, where B is the bandwidth of each channel, and the send and receive bandwidths can be adjusted to any values such that N*B≧(S*B+R*B), on an as-needed basis depending on the processing algorithms being executed.

Abstract: A reconfigurable processor architecture. A reconfigurable processor is an array of a multiplicity of various functional elements, between which the interconnections may be programmably configured. The inventive processor is implemented on a single substrate as a network of clusters of elements. Each cluster includes a crossbar switching node to which a plurality of elements is connected via ports. Additional ports on the crossbar switching node connect to the switching nodes of nearest neighbor clusters. The crossbar switching nodes allow pathways to be programmably set between any of the ports, and any pathway may be set to be either registered or unregistered. The use of clusters of processing elements allows complete freedom of local connectivity for effective configuration of many different processing functions. Wide area interconnection is more restricted, but, since it is less used, does not significantly restrict configurability.

Abstract: An automated system and method for testing a sensor by evaluating the output thereof with respect to a known target. The advantageous method includes the step of acquiring an output signal from the sensor in response to a known target, said output including signature signal S, random noise N.sub.R and fixed pattern noise N.sub.FP. Next, the sensor output signal is processed to provide a first signal which includes essentially signature signal S and fixed pattern noise N.sub.FP, a second signal which includes essentially random noise N.sub.R and a third signal which includes essentially fixed pattern noise N.sub.FP. The third signal is adaptively filtered to provide a filtered signal fixed pattern noise signal N'.sub.FP. The filtered signal N'.sub.FP is subtracted from the first signal to extract a signature S. In a particular embodiment, the signature is processed to acquire a modulation transfer function and a signal peak baseline therefrom.

Abstract: A method for measuring and quantifying clutter, and target detection and tracking systems that employs wavelet-based clutter quantification to generate a clutter number and a signal-to-clutter ratio derived therefrom to achieve improved target detection performance. The method processes video signals representative of an image scene containing a target and background clutter to provide for more accurate tracking of the target by a tracker(s). The method comprises processing the video signals to compute a wavelet clutter number, processing the video signals to compute a signal-to clutter ratio using the wavelet clutter number, and generating a pointer to a lookup table that sets parameters and selects the tracker that is to be used to track the target based upon the computed signal-to clutter ratio.

Abstract: A scene based nonuniformity correction method (40) that computes and applies offset correction errors to a video signal corresponding to an image derived from a imaging sensor (11). A video signal derived from the sensor (11) is processed such that a vector representing offset correction terms is formed, and this vector is initially set to zero. Each element in this vector represents a correction term for a particular detector of the sensor (11). The vector is applied to each pixel of the image by a processor (13) as the pixels are read from the sensor (11). To measure the offset error, the image is separated into vertically oriented regions, each comprising a plurality of channels. The average of each channel within a region is computed (42), and a set of region vectors is foraged, such that there is one region vector for each region. Each region vector is then globally high-pass filtered and then edges larger than a predefined threshold are detected (43), and marked (44).

Abstract: An imaging system including a scanning linear detector array is calibrated with the aid of a source of radiation to provide uniformity in gain among the various detectors of the array. A first memory is provided for storing a map of the source obtained by a scanning through a succession of parallel line scans by means of a single one of the detectors, the detector array being offset between the successive line scans to enable the single detector to perform all of the line scans. A second memory is provided to store an image of the source provided by a scanning by all of the detectors along their respective scan lines. The data obtained in each line scan in each of the memories is averaged. Then, the average value for a scan line stored in the second memory is divided by the average value of the same scan line appearing in the first memory to provide a ratio for each scan line. The ratio is the gain of the detector of the scan line relative to the gain of the first detector.

Abstract: Techniques for calibrating differential temperature sources including the use of a calibrated infrared imaging sensor having an associated calibrated temperature function that is expressed as a function of a predetermined calculated parameter indicative of the actual differential temperature of a differential temperature source. The temperature source being calibrated is thermally imaged at different indicated differential temperatures to provide thermal images associated with the indicated temperatures, and such images are processed to define the calculated parameter as as function of indicated temperature. The calculated parameter function is substituted in the calibrated temperature function to provide a calibrated temperature function that is expressed as a function of indicated differential temperature.