Abstract: An apparatus and technique off-loads responsibility for maintaining order among requests directed to a same address on a split transaction bus from a processor to a split transaction bus controller, thereby increasing the performance of the processor. The present invention comprises an ordering circuit that enables the controller to defer issuing a subsequent (write) request directed to an address on the bus until a previous (read) request directed to the same address completes. By off-loading responsibility for maintaining order among requests from the processor to the controller, the invention enhances performance of the processor since the processor may proceed with program execution without having to stall to ensure such ordering. The ordering circuit maintains ordering in an efficient manner that is transparent to the processor.

Abstract: A sequence control mechanism enables out-of-order processing of contexts by processors of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The processors of the engine are preferably arrayed as a plurality of rows or clusters embedded between input and output buffers, wherein each cluster of processors is configured to process contexts in a first in, first out (FIFO) synchronization order. However, the sequence control mechanism allows out-of-order context processing among the clusters of processors, while selectively enforcing FIFO synchronization ordering among those clusters on an as needed basis, i.e., for certain contexts. As a result, the control mechanism reduces undesired processing delays among those processors.

Abstract: A dynamic addressing technique mirrors data across multiple banks of a memory resource. Information stored in the memory banks is organized into separately addressable blocks, and memory addresses include a mirror flag. To write information mirrored across two memory banks, a processor issues a single write transaction with the mirror flag asserted. A memory controller detects that the mirror flag is asserted and, in response, waits for both memory banks to become available. At that point, the memory controller causes the write to be performed at both banks. To read data that has been mirrored across two memory banks, the processor issues a read with the mirror flag asserted. The memory controller checks the availability of both banks having the desired information. If either bank is available, the read request is accepted and the desired data is retrieved from the available bank and returned to the processor.

Abstract: A system and method maintains order among a plurality of threads in a multi-threaded processing system. The processing system, which may be disposed at an intermediate network device, has a plurality of processors each supporting a plurality of threads. The ordering system includes a dispatcher that assigns work, such as the processing of received packets to free threads, an order manager that keeps track of the relative order of the threads, and a thread client associated with each thread for enforcing the determined order. Packets to be processed by the processing system are assigned to an initial order group by the order manager based on a selected attribute, and those packets sharing the same attribute value are assigned to the same order group. During processing, a thread may request reassignment to other order groups in response to other attributes of the packets.

Abstract: Virtual Local Area Network (VLAN) trunking over Asychronous Transfer Mode (ATM) Permanent Virtual Circuits (PVC), defined as VTAP, allows for aggregation of multiple VLAN traffic into a single data pipe in a Wide Area Network (WAN) environment. The largest benefit for the user is that a single PVC can be utilized to aggregate all of their VLAN traffic between two sites. Packets to be transmitted between two switches are first encapsulated with a VTAP header that contains pertinent information as to allow the receiving switch to process and forward the packet at the switch. Certain information contained in the VTAP is also used to determine the virtual path identifier/virtual channel identifier (VPI/VCI) of the destination switch wherein the packet is segmented into ATM cells having VPI/VCI prefixed to it for forwarding via the ATM network.

Abstract: An apparatus and technique off-loads responsibility for maintaining order among requests issued over a split transaction bus from a processor to a split transaction bus controller, thereby increasing the performance of the processor. A logic circuit enables the controller to defer issuing a subsequent (write) request directed to an address on the bus until all pending (read) requests complete. By off-loading responsibility for maintaining order among requests from the processor to the controller, the invention enhances performance of the processor since the processor may proceed with program execution without having to stall to ensure such ordering. The logic circuit maintains the order of the requests in an efficient manner that is transparent to the processor.

Abstract: A computer system stores packet data and reduces the number of Read-Modify-Write (RMW) operations. An attribute is configured to specify a mode of operation that instructs the processor to perform a RMW operation, or to pad the packet data to over-write a memory line. A buffer defines the memory lines. Each memory line has a discrete number of bytes. The processor addresses the buffer with a memory address register. The attribute is a new bit in the memory address register. The attribute is configured to specify a mode of operation that instructs the processor to pad the packet data to be equal to one or more complete, full memory lines so that the padded packet data are stored only in complete, full memory lines, rather than to do an expensive RMW operation. The attribute may be a new bit added to the memory address register.

Abstract: A technique efficiently transports token ring (TR) frames over trunks interconnecting switches of a distributed TR bridge. The TR bridge is characterized by a logical switch fabric that is distributed among the interconnected switches by the trunks, which are preferably interswitch link (ISL) trunks. Each switch includes a Bridge Relay Function (BRF) coupled to a plurality of Concentrator Relay Functions (CRFs) having a plurality of ports for receiving TR frames over TR segments. The BRF and CRF of the distributed TR bridge operate according to a 2-tier switching model wherein each CRF and BRF is assigned an individual virtual local area network identifier. The technique encapsulates the TR frames in a TR-ISL protocol format that accomodates differences in formats of various TR frames and that comports with the 2-tier switching model of the distributed TR bridge.

Abstract: A Distributed Ring Protocol (DRiP) arrangement includes a database and protocol for maintaining and distributing information within a distributed token ring (TR) bridge having a logical switch fabric that is distributed over a TR switching network of switches interconnected by trunk links, such as Inters witch Link (ISL) trunks. The DRiP information is used by switches within the ISL switched fabric to determine the status (configured and/or activated) and association (within a switch) of ports of the distributed bridge.

Abstract: A group and virtual locking mechanism (GVLM) addresses two classes of synchronization present in a system having resources that are shared by a plurality of threads of execution: (1) synchronization of the multi-access shared resources; and (2) simultaneous requests for the shared resources. Broadly stated, the novel GVLM comprises a lock controller function associated with each thread of execution, and lock instructions executed by the threads that manipulate the lock controller to create a tightly integrated arrangement for issuing lock requests to the shared resources. The plurality of threads of execution may each execute in a different processor. Alternatively, the plurality of threads of execution may each execute in a single processor.

Abstract: An inter-chip communication (ICC) mechanism enables any processor in a pipelined arrayed processing engine to communicate directly with any other processor of the engine over a low-latency communication path. The ICC mechanism includes a unidirectional control plane path that is separate from a data plane path of the engine and that accommodates control information flow among the processors. The mechanism thus enables inter-processor communication without sending messages over the data plane communication path extending through processors of each pipeline.

Abstract: A backup CRF VLAN arrangement provides an alternate, redundant path for traffic between undistributed Concentrator Relay Functions (CRFs) located on separate switches interconnected by trunk links of a distributed token ring bridge. The backup CRF virtual local area network (VLAN) arrangement defines a backup network path which may be utilized if a primary active path is not a valid path to a backup network. Notably, the backup network comprises a special type of CRF that is distributed among the switches, but that has only one port active at any given time.

Abstract: A distributed token ring (TR) bridge has a logical switch fabric that is distributed over a TR switching network of switches interconnected by trunk links. The distributed TR bridge includes a plurality of TR switches, each having a Bridge Relay Function (BRF) logically coupled to at least one Concentrator Relay Function (CRF). Distribution of the switch fabric essentially comprises logically distributing the BRF function among the network of switches.

Abstract: A LAN interconnect device includes a plurality of Frame Processing Units (FPUs) for coupling each port of the device to a switch fabric. Each one of the Frame Processing Units includes an input section with input logic which prepares LS Headers and appends each one to a block of the frame as the block is forwarded to the switch fabric. The FPU, also, includes an output section with copy logic for copying and assembling frames to be forwarded to devices connected to the port. The copy decision is based upon the LS Header and configuration information in the port.

Abstract: A group and virtual locking mechanism (GVLM) addresses two classes of synchronization present in a system having resources that are shared by a plurality of processors: (1) synchronization of the multi-access shared resources; and (2) simultaneous requests for the shared resources. The system is a programmable processing engine comprising an array of processor complex elements, each having a microcontroller processor. The processor complexes are preferably arrayed as rows and columns. Broadly stated, the novel GVLM comprises a lock controller function associated with each column of processor complexes and lock instructions executed by the processors that manipulate the lock controller to create a tightly integrated arrangement for issuing lock requests to the shared resources.

Abstract: A dynamic address mapping technique eliminates contention to memory resources of a symmetric multiprocessor system having a plurality of processors arrayed as a processing engine. The technique defines two logical-to-physical address mapping modes that may be simultaneously provided to the processors of the arrayed processing engine to thereby present a single contiguous address space for accessing individual memory locations, as well as memory strings, within the memory resources. These addressing modes include a bank select mode and a stream mode.

Abstract: A multi-port switching device architecture decouples decode logic circuitry of each port of a network switch from its respective state machine logic circuitry and organizes the state machine logic as pools of transmit/receive engine resources that are shared by each of the decode logic circuits. Intermediate priority logic of the switching device cooperates with the decode logic and pooled resources to allocate frames among available resources in accordance with predetermined ordering and fairness policies. These policies prevent misordering of frames from a single source while ensuring that all ports in the device are serviced fairly.

Abstract: An improved spanning tree protocol for use by token ring intermediate devices having one or more Concentrator Relay Function (CRF) entities and associated Bridge Relay Function (BRF) entities. Each CRF and BRF entity preferably includes a spanning tree engine and corresponding database for individually executing an instance of the spanning tree algorithm and is configured to select a different Bridge Protocol Data Unit (BPDU) message type for use in executing its respective spanning tree algorithm. The selection of BPDU message type by the CRF and BRF spanning tree engines preferably depends on the routing configuration of the associated CRF. The selection of BPDU message type by the CRF entities assures that they are dropped by legacy intermediate devices and only acted upon by the originating CRF or another CRF coupled thereto.

Abstract: A device for interconnecting Local Area Networks (LANs) includes ports for attaching LAN segments and port modules for connecting the ports to a switch fabric. Each of the port modules include a mechanism which searches the Routing Information (RI) field of a Received frame to detect at least two Triplets (a minimum configuration for a LAN segment) indicating a Source path from an originator user and a Destination path to a destination user. The Triplet (single or in combination) is used to access a database (tables) which identifies the Port of Exit (POE) through which the frame is to be routed.

Abstract: Controller triple modular redundancy is substantially achieved and reliability improved in a system having duplicate controllers that serve peripheral units. Both controllers detect suspected faults in itself and in the other controller. A peripheral unit that suspects a faulty active controller requests a switch of the active controller. A voting circuit processes votes from the controllers and the active controller switch signal from the peripheral units to select the active controller. The signaling paths between the controllers used to convey votes and active controller information are duplicated. The signals on these signaling paths convey information by using oscillating signals of different frequencies.