Patents by Inventor Kenneth J. Stein
Kenneth J. Stein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240006517Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.Type: ApplicationFiled: September 19, 2023Publication date: January 4, 2024Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
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Patent number: 11855196Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.Type: GrantFiled: October 25, 2021Date of Patent: December 26, 2023Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
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Patent number: 11855195Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.Type: GrantFiled: October 25, 2021Date of Patent: December 26, 2023Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
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Publication number: 20230129914Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted “T” shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.Type: ApplicationFiled: October 25, 2021Publication date: April 27, 2023Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
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Publication number: 20230127768Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises mono-crystal silicon based material; an intrinsic base under the emitter region and comprising semiconductor material; and an extrinsic base surrounding the emitter and over the intrinsic base.Type: ApplicationFiled: October 25, 2021Publication date: April 27, 2023Inventors: Xinshu Cai, Shyue Seng Tan, Vibhor Jain, John J. Pekarik, Kien Seen Daniel Chong, Yung Fu Chong, Judson R. Holt, Qizhi Liu, Kenneth J. Stein
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Patent number: 8564074Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.Type: GrantFiled: November 29, 2011Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Terence B. Hook, Vijay Narayanan, Jay M. Shah, Melanie J. Sherony, Kenneth J. Stein, Helen H. Wang, Chendong Zhu
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Publication number: 20130134545Abstract: A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate including: a high-K dielectric region; a blocking region disposed against at least one surface of the high-K dielectric region and adapted to form an oxidized layer in response to exposure to oxygen; and an oxygen rich region disposed against the blocking region such that the blocking region is interposed between the oxygen rich region and the high-K dielectric region.Type: ApplicationFiled: November 29, 2011Publication date: May 30, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Terence B. Hook, Vijay Narayanan, Jay M. Shah, Melanie J. Sherony, Kenneth J. Stein, Helen H. Wang, Chendong Zhu
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Patent number: 8106462Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.Type: GrantFiled: January 14, 2010Date of Patent: January 31, 2012Assignees: International Business Machines Corporation, Freescale Semiconductor, Inc., Infineon Technologies North America Corp., Chartered Semiconductor Manufacturing Ltd.Inventors: Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony, Kenneth J. Stein, Haizhou Yin, Franck Arnaud, Jin-Ping Han, Laegu Kang, Yong Meng Lee, Young Way Teh, Voon-Yew Thean, Da Zhang
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Patent number: 8062951Abstract: An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a <100> crystal orientation. An effective width of an FET device formed in the RX region may be increased, therefore performance may be improved with same density. Isolation may not be degraded since RX-to-RX distance is same at bottom. Junction capacitance may be reduced since part of the RX is on STI.Type: GrantFiled: December 10, 2007Date of Patent: November 22, 2011Assignee: International Business Machines CorporationInventors: Xiangdong Chen, Kenneth J. Stein, Thomas A. Wallner
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Patent number: 8004060Abstract: A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.Type: GrantFiled: November 29, 2007Date of Patent: August 23, 2011Assignee: International Business Machines CorporationInventors: Deok-kee Kim, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran, Kenneth J. Stein
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Publication number: 20110169096Abstract: An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-producing layer on the first transistor and the second transistor, and a second stress-producing layer on the first stress-producing layer over the first transistor and the second transistor. The first stress-producing layer applies tensile strain force on the first transistor and the second transistor. The second stress-producing layer applies compressive strain force on the first stress-producing layer, the first transistor, and the second transistor.Type: ApplicationFiled: January 14, 2010Publication date: July 14, 2011Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, FREESCALE SEMICONDUCTOR, INC., INFINEON TECHNOLOGIES NORTH AMERICA CORP., CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Xiangdong Chen, Weipeng Li, Anda C. Mocuta, Dae-Gyu Park, Melanie J. Sherony, Kenneth J. Stein, Haizhou Yin, Franck Arnaud, Jin-Ping Han, Laegu Kang, Yong Meng Lee, Young Way Teh, Voon-Yew Thean, Da Zhang
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Patent number: 7867839Abstract: Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).Type: GrantFiled: July 21, 2008Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: Xiangdong Chen, Jong Ho Lee, Weipeng Li, Dae-Gyu Park, Kenneth J. Stein, Voon-Yew Thean
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Patent number: 7829427Abstract: A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.Type: GrantFiled: November 5, 2009Date of Patent: November 9, 2010Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Panayotis C. Andricacos, John M. Cotte, Hariklia Deligianni, John H. Magerlein, Kevin S. Petrarca, Kenneth J. Stein, Richard P. Volant
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Publication number: 20100047990Abstract: A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.Type: ApplicationFiled: November 5, 2009Publication date: February 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Panayotis C. Andricacos, John M. Cotte, Hariklia Deligianni, John H. Magerlein, Kevin S. Petrarca, Kenneth J. Stein, Richard P. Volant
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Publication number: 20100013021Abstract: Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).Type: ApplicationFiled: July 21, 2008Publication date: January 21, 2010Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, FREESCALE SEMICONDUCTOR INC., SAMSUNG ELECTRONICS CO., LTD.Inventors: Xiangdong Chen, Jong Ho Lee, Weipeng Li, Dae-Gyu Park, Kenneth J. Stein, Voon-Yew Thean
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Patent number: 7638406Abstract: A method of forming an inductor. The method includes: forming a dielectric layer on a substrate; forming a lower trench in the dielectric layer; forming a liner in the lower trench and on the dielectric layer; forming a Cu seed layer over the liner; forming a resist layer on the Cu seed layer; forming an upper trench in the resist layer; electroplating Cu to completely fill the lower trench and at least partially fill the upper trench; removing the resist layer; selectively forming a passivation layer on all exposed Cu surfaces; selectively removing the Cu seed layer from regions of the liner; and removing the thus exposed regions of the liner from the dielectric layer, wherein a top surface of the inductor extends above a top surface of the dielectric layer, the passivation layer remaining on regions of sidewalls of the inductor above the top surface of the dielectric layer.Type: GrantFiled: December 28, 2005Date of Patent: December 29, 2009Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Panayotis C. Andricacos, John M. Cotte, Hariklia Deligianni, John H. Magerlein, Kevin S. Petrarca, Kenneth J. Stein, Richard P. Volant
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Publication number: 20090146263Abstract: An epitaxial layer of silicon (Si) or silicon-germanium (SiGe) extends over the edge of silicon trench isolation (STI), thereby increasing the effective width of an active silicon region (RX) bordered by the STI. The RX region may have a <100> crystal orientation. An effective width of an FET device formed in the RX region may be increased, therefore performance may be improved with same density. Isolation may not be degraded since RX-to-RX distance is same at bottom. Junction capacitance may be reduced since part of the RX is on STI.Type: ApplicationFiled: December 10, 2007Publication date: June 11, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xiangdong Chen, Kenneth J. Stein, Thomas A. Wallner
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Publication number: 20090141533Abstract: A metal layer and a semiconductor layer are sequentially deposited on a substrate. The semiconductor layer and the metal layer are lithographically patterned to form a stack of a semiconductor portion and a metal gate portion, which is preferably performed concurrently with formation of at least one metal gate stack. In one embodiment, the size of the semiconductor portion is reduced and a metal semiconductor alloy portion is formed on the semiconductor portion by metallization. In a first electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the metal semiconductor alloy portion and the metal gate portion. In another embodiment, two disjoined metal semiconductor alloy portions are formed on the semiconductor portion. In a second electrical antifuse formed thereby, the metal semiconductor alloy portion may be electromigrated to form a short between the two previously disjoined metal semiconductor alloy portions.Type: ApplicationFiled: November 29, 2007Publication date: June 4, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Deok-kee Kim, Chandrasekharan Kothandaraman, Dan Moy, Norman W. Robson, John M. Safran, Kenneth J. Stein
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Patent number: 7354872Abstract: Methods of forming a high dielectric constant dielectric layer are disclosed including providing a process chamber including a holder for supporting a substrate, introducing a first gas comprising a high dielectric constant (Hi-K) dielectric precursor and an oxygen (O2) oxidant into the process chamber to form a first portion of the high dielectric constant dielectric layer on the substrate, and switching from a flow of the first gas to a flow of a second gas comprising the Hi-K dielectric precursor and an ozone (O3) oxidant to form a second portion of the high dielectric constant dielectric layer on the first portion. In an alternative embodiment, another portion can be formed on the second portion using the oxygen oxidant. The invention increases throughput by at least 20% without reliability or leakage degradation and without the need for additional equipment.Type: GrantFiled: May 26, 2005Date of Patent: April 8, 2008Assignee: International Business Machines CorporationInventors: Douglas D. Coolbaugh, Ebenezer E. Eshun, Kenneth J. Stein, Kunal Vaed
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Patent number: 7193500Abstract: An integrated circuit includes a bilayer thin film resistor in which the lower layer is a seed layer that controls the crystal structure of the upper layer. The thickness of the lower layer and the thickness of the upper layer may be chosen to form a resistor with a TCR having a design value.Type: GrantFiled: September 20, 2004Date of Patent: March 20, 2007Assignee: International Business Machines CorporationInventors: Anil K. Chinthakindi, Anita Madan, Kenneth J. Stein, Kwong Hon Wong