Patents by Inventor Kenneth Jaramillo
Kenneth Jaramillo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240104040Abstract: An apparatus for determining a disconnection of a device from a bus, the apparatus comprising: a detection unit configured to periodically poll the bus, to detect an occurrence of an indicator of disconnection; and a handling unit configured to, in response to detecting the occurrence of an indicator of disconnection a predetermined number of times within a predetermined interval, make a determination that the device is disconnected from the bus. A method for determining a disconnection of a device from a bus is also presented.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventor: Kenneth Jaramillo
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Publication number: 20240070100Abstract: One example discloses a communications device, including: an interface port, configured to couple the communications device to another device; a transmitter configured to transmit signals on the interface port; a receiver configured to receive signals on the interface port; and a switch configured to short the interface port to a reference potential after the transmitter transmits signals on the interface port.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventors: Siamak Delshadpour, Kenneth Jaramillo, Regis Santonja
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Patent number: 11671289Abstract: Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.Type: GrantFiled: September 14, 2021Date of Patent: June 6, 2023Assignee: NXP USA, Inc.Inventors: Ranjeet Kumar Gupta, Siamak Delshadpour, Kenneth Jaramillo
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Publication number: 20230079021Abstract: Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.Type: ApplicationFiled: September 14, 2021Publication date: March 16, 2023Inventors: Ranjeet Kumar GUPTA, Siamak Delshadpour, Kenneth Jaramillo
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Patent number: 11573268Abstract: Various embodiments relate to a skew detector circuit, including: a logic circuit having two inputs configured to generate a logic 1 output when the two inputs have a logic 0 value and generator a logic 0 output when the two input have a logic 1 value; a first level shifter configured to increase the output of the logic circuit to a higher voltage; a second level shifter configured to increase the output of the first level shifter to a higher voltage; and a voltage regulator configured to produce a first voltage for the logic circuit, a second voltage for the first level shifter, and a third voltage for the second level shift.Type: GrantFiled: September 14, 2021Date of Patent: February 7, 2023Assignee: NXP USA, Inc.Inventors: Siamak Delshadpour, Xu Zhang, Xiaoqun Liu, Kenneth Jaramillo
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Patent number: 10209730Abstract: Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.Type: GrantFiled: November 23, 2017Date of Patent: February 19, 2019Assignee: NXP B.V.Inventors: Chiahung Su, Madan Mohan Reddy Vemula, Abjijeet Chandrakant Kulkarni, Kenneth Jaramillo, Siamak Delshadpour, Xueyang Geng
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Patent number: 10114782Abstract: A universal serial bus (USB) circuit includes a USB interface configured to transmit and receive power and data, a random number generator circuit configured to generate a random number, and a controller configured to receive the random number and to select a dual role port (DRP) duty cycle and to select a DRP duration based upon the random number, wherein the DRP duty cycle time and DRP duration are used when connecting a USB type-C DRP device to another USB type-C DRP device.Type: GrantFiled: September 27, 2016Date of Patent: October 30, 2018Assignee: NXP B.V.Inventors: Abhijeet Chandrakant Kulkarni, Kenneth Jaramillo
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Patent number: 10088884Abstract: A protocol can specifie a power-sourcing voltage range that indicates power sourcing capabilities. Additional power sourcing capabilities can be communicated using voltage variations within the power-sourcing voltage range. A power-sourcing device can provide power to an external power-sinking device over a wired connection containing a plurality of wires. A voltage control circuit can be configured to drive a voltage over a wire of the plurality of wires. Processing circuitry can communicate, using the voltage control circuit, first power-sourcing capabilities to the external power-sinking device by setting the voltage over the wire to a value within the power-sourcing voltage range. The processing circuitry can also communicate, using the voltage control circuit, the additional power sourcing capabilities of the power-sourcing device using voltage variations on the wire, the voltage variations maintaining voltage on the wire within the power-sourcing voltage range.Type: GrantFiled: October 23, 2015Date of Patent: October 2, 2018Assignee: NXP B.V.Inventors: Kenneth Jaramillo, Madan Mohan Reddy Vemula, Sharad Murari, Abhijeet Chandrakant Kulkarni, Krishnan Tiruchi Natarajan
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Patent number: 9998276Abstract: Disclosed is a method of controlling a USB Power Delivery System including determining whether at least a predetermined length of initial bits of a message is received, turning on a clock when the predetermined length is received, determining whether the message has stopped, starting a counter when the message has stopped, determining whether a count value of the counter has reached a predetermined value, and turning off the clock when the predetermined count value has been reached.Type: GrantFiled: September 27, 2016Date of Patent: June 12, 2018Assignee: NXP B.V.Inventors: Abhijeet Chandrakant Kulkarni, Kenneth Jaramillo, Siamak Delshadpour
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Publication number: 20180095490Abstract: Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.Type: ApplicationFiled: November 23, 2017Publication date: April 5, 2018Inventors: Chiahung Su, Madan Mohan Reddy Vemula, Abjijeet Chandrakant Kulkarni, Kenneth Jaramillo, Siamak Delshadpour, Xueyang Geng
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Publication number: 20180091289Abstract: Disclosed is a method of controlling a USB Power Delivery System including determining whether at least a predetermined length of initial bits of a message is received, turning on a clock when the predetermined length is received, determining whether the message has stopped, starting a counter when the message has stopped, determining whether a count value of the counter has reached a predetermined value, and turning off the clock when the predetermined count value has been reached.Type: ApplicationFiled: September 27, 2016Publication date: March 29, 2018Inventors: Abhijeet Chandrakant KULKARNI, Kenneth JARAMILLO, Siamak DELSHADPOUR
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Publication number: 20180089123Abstract: Disclosed is a universal serial bus (USB) circuit, comprising including a USB interface configured to transmit and receive power and data, a random number generator circuit configured to generate a random number, and a controller configured to receive the random number and to select a dual role port (DRP) duty cycle and to select a DRP duration based upon the random number, wherein the DRP duty cycle time and DRP duration are used when connecting a USB type-C DRP device to another USB type-C DRP device.Type: ApplicationFiled: September 27, 2016Publication date: March 29, 2018Inventors: Abhijeet Chandrakant KULKARNI, Kenneth JARAMILLO
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Publication number: 20170192446Abstract: Low power solutions can be provided in a serial bus system with a logic controller circuit. The logic controller circuit can include analog circuitry that includes a plurality of analog components and trimming circuitry for configuring the analog components. Digital circuitry can be configured to switch between an active mode and a hibernation mode, wherein the hibernation mode consumes less current than the active mode. A voltage regulator circuit can be configured to generate a regulated voltage from a supply voltage. A reset generation circuit can be configured to determine that the supply voltage has reached a first threshold voltage level and enable the voltage regulator circuit. When the regulated voltage has reached a second threshold voltage level and the supply voltage has reached a third threshold voltage level, the digital circuitry can be switched to the active mode.Type: ApplicationFiled: January 6, 2016Publication date: July 6, 2017Inventors: Chiahung Su, Madan Mohan Reddy Vemula, Abhijeet Chandrakant Kulkarni, Kenneth Jaramillo
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Publication number: 20170115711Abstract: A protocol can specifie a power-sourcing voltage range that indicates power sourcing capabilities. Additional power sourcing capabilities can be communicated using voltage variations within the power-sourcing voltage range. A power-sourcing device can provide power to an external power-sinking device over a wired connection containing a plurality of wires. A voltage control circuit can be configured to drive a voltage over a wire of the plurality of wires. Processing circuitry can communicate, using the voltage control circuit, first power-sourcing capabilities to the external power-sinking device by setting the voltage over the wire to a value within the power-sourcing voltage range. The processing circuitry can also communicate, using the voltage control circuit, the additional power sourcing capabilities of the power-sourcing device using voltage variations on the wire, the voltage variations maintaining voltage on the wire within the power-sourcing voltage range.Type: ApplicationFiled: October 23, 2015Publication date: April 27, 2017Inventors: Kenneth Jaramillo, Madan Mohan Reddy Vemula, Sharad Murari, Abhijeet Chandrakant Kulkarni, Krishnan Tiruchi Natarajan
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Patent number: 8769343Abstract: Consistent with embodiments of the present disclosure, a method involves a redriver circuit with compliance test mode features. A redriver circuit is configured to process received compliance patterns for a compliance test mode. A compliance test mode is detected by a redriver circuit having a first input port and a second input port. The redriver detects the presence of a remote receiver termination on both input ports, monitors both input ports to detect received data and enters compliance test mode in response to no received data being detected on the input ports for a set period of time. Compliance patterns are tracked by monitoring for valid signal levels on the second input port. De-emphasis is controlled on at least one input port in response thereto.Type: GrantFiled: June 20, 2011Date of Patent: July 1, 2014Assignee: NXP B.V.Inventor: Kenneth Jaramillo
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Patent number: 8645724Abstract: Consistent with embodiments of the present disclosure a redriver circuit is provided for a first and a second serial-unidirectional communications channel. The redriver circuit conditions received data signals by adjusting signal properties to correct for signal level attenuation and noise. The conditioned data signals are transmitted to corresponding outputs of the channels. The redriver circuit disables, in response to a first enable signal being inactive, current drawing circuitry of components for both channels on a common side of the redriver. The redriver circuit disables, in response to a second enable signal being inactive, current drawing circuitry of components for both channels on the other side of the redriver.Type: GrantFiled: June 3, 2011Date of Patent: February 4, 2014Assignee: NXP B.V.Inventor: Kenneth Jaramillo
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Patent number: 8380912Abstract: Consistent with an example embodiment a repeater device is provided for handling signal transmissions, in particular in a DisplayPort environment. The repeater is to be coupled with an upstream device and a downstream device, the repeater being adapted for transmitting signals received from the upstream device to the downstream device and for conditioning the signals before transmission. The repeater is configured to provide a transparent communication path between the upstream device and the downstream device for DPCD access transactions belonging to a second group of DPCD access transactions. For DPCD access transactions belonging to a first group of DPCD access transaction, the repeater is configured to process the DPCD access transactions by accessing one or more DPCD registers included in the repeater.Type: GrantFiled: September 24, 2010Date of Patent: February 19, 2013Assignee: NXP B.V.Inventor: Kenneth Jaramillo
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Publication number: 20120317446Abstract: Consistent with embodiments of the present disclosure, a method involves a redriver circuit with compliance test mode features. A redriver circuit is configured to process received compliance patterns for a compliance test mode. A compliance test mode is detected by a redriver circuit having a first input port and a second input port. The redriver detects the presence of a remote receiver termination on both input ports, monitors both input ports to detect received data and enters compliance test mode in response to no received data being detected on the input ports for a set period of time. Compliance patterns are tracked by monitoring for valid signal levels on the second input port. De-emphasis is controlled on at least one input port in response thereto.Type: ApplicationFiled: June 20, 2011Publication date: December 13, 2012Inventor: Kenneth Jaramillo
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Publication number: 20120311359Abstract: Consistent with embodiments of the present disclosure a redriver circuit is provided for a first and a second serial-unidirectional communications channel. The redriver circuit conditions received data signals by adjusting signal properties to correct for signal level attenuation and noise. The conditioned data signals are transmitted to corresponding outputs of the channels. The redriver circuit disables, in response to a first enable signal being inactive, current drawing circuitry of components for both channels on a common side of the redriver. The redriver circuit disables, in response to a second enable signal being inactive, current drawing circuitry of components for both channels on the other side of the redriver.Type: ApplicationFiled: June 3, 2011Publication date: December 6, 2012Inventor: Kenneth Jaramillo
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Publication number: 20120079162Abstract: Consistent with an example embodiment a repeater device is provided for handling signal transmissions, in particular in a DisplayPort environment. The repeater is to be coupled with an upstream device and a downstream device, the repeater being adapted for transmitting signals received from the upstream device to the downstream device and for conditioning the signals before transmission. The repeater is configured to provide a transparent communication path between the upstream device and the downstream device for DPCD access transactions belonging to a second group of DPCD access transactions. For DPCD access transactions belonging to a first group of DPCD access transaction, the repeater is configured to process the DPCD access transactions by accessing one or more DPCD registers included in the repeater.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Applicant: NXP B.V.Inventor: Kenneth JARAMILLO