Abstract: Techniques for time-aware remote data transfers. A time may be associated with a remote direct memory access (RDMA) operation in a translation protection table (TPT). The RDMA operation may be permitted or restricted based on the time in the TPT.

Abstract: Technologies for an accelerator interface over Ethernet are disclosed. In the illustrative embodiment, a network interface controller of a compute device may receive a data packet. If the network interface controller determines that the data packet should be pre-processed (e.g., decrypted) with a remote accelerator device, the network interface controller may encapsulate the data packet in an encapsulating network packet and send the encapsulating network packet to a remote accelerator device on a remote compute device. The remote accelerator device may pre-process the data packet (e.g., decrypt the data packet) and send it back to the network interface controller. The network interface controller may then send the pre-processed packet to a processor of the compute device.

Abstract: Technologies for remote direct memory access (RDMA) congestion control include a requester device and a responder device in communication over an Ethernet network. The requester device sends routable RDMA packets to the responder device over the Ethernet network. The packets may be RDMA over Converged Ethernet version 2 (RoCEv2) packets. The responder device determines whether any of the received packets have been marked by the network with a congestion encountered codepoint. If so, the responder device sends an acknowledgment packet with an express congestion notification bit set in the RDMA base transport header. The requester device updates a congestion window as a function of a number of congested packets acknowledged and a total number of packets acknowledged. Those operations may be performed by a network controller of each of the requester device and the responder device. Other embodiments are described and claimed.

Abstract: Technologies for remote direct memory access (RDMA) congestion control include a requester device and a responder device in communication over an Ethernet network. The requester device sends routable RDMA packets to the responder device over the Ethernet network. The packets may be RDMA over Converged Ethernet version 2 (RoCEv2) packets. The responder device determines whether any of the received packets have been marked by the network with a congestion encountered codepoint. If so, the responder device sends an acknowledgment packet with an express congestion notification bit set in the RDMA base transport header. The requester device updates a congestion window as a function of a number of congested packets acknowledged and a total number of packets acknowledged. Those operations may be performed by a network controller of each of the requester device and the responder device. Other embodiments are described and claimed.

Abstract: Technologies for an accelerator interface over Ethernet are disclosed. In the illustrative embodiment, a network interface controller of a compute device may receive a data packet. If the network interface controller determines that the data packet should be pre-processed (e.g., decrypted) with a remote accelerator device, the network interface controller may encapsulate the data packet in an encapsulating network packet and send the encapsulating network packet to a remote accelerator device on a remote compute device. The remote accelerator device may pre-process the data packet (e.g., decrypt the data packet) and send it back to the network interface controller. The network interface controller may then send the pre-processed packet to a processor of the compute device.

Abstract: An apparatus is provided, for performing a direct memory access (DMA) operation between a host memory in a first server and a network adapter. The apparatus includes a host frame parser and a protocol engine. The host frame parser is configured to receive data corresponding to the DMA operation from a host interface, and is configured to insert markers on-the-fly into the data at a prescribed interval and to provide marked data for transmission to a second server over a network fabric. The protocol engine is coupled to the host frame parser. The protocol engine is configured to direct the host frame parser to insert the markers, and is configured to specify a first marker value and an offset value, whereby the host frame parser is enabled to locate and insert a first marker into the data.

Abstract: A computer system such as a server pipelines RNIC interface (RI) management/control operations such as memory registration operations to hide from network applications the latency in performing RDMA work requests caused in part by delays in processing the memory registration operations and the time required to execute the registration operations themselves. A separate QP-like structure, called a control QP (CQP), interfaces with a control processor (CP) to form a control path pipeline, separate from the transaction pipeline, which is designated to handle all control path traffic associated with the processing of RI control operations. This includes memory registration operations (MR OPs), as well as the creation and destruction of traditional QPs for processing RDMA transactions. Once the MR OP has been queued in the control path pipeline of the adapter, a pending bit is set which is associated with the MR OP.

Abstract: A flexible arrangement allows a single arrangement of Ethernet channel adapter (ECA) hardware functions to appear as needed to conform to various operating system deployment models. A PCI interface presents a logical model of virtual devices appropriate to the relevant operating system. Mapping parameters and values are associated with the packet streams to allow the packet streams to be properly processed according to the presented logical model and needed operations. Mapping occurs at both the host side and at the network side to allow the multiple operations of the ECA to be performed while still allowing proper delivery at each interface.

Abstract: A mechanism for performing RDMA operations over a network fabric. Apparatus includes transaction logic to process work queue elements, and to accomplish the RDMA operations over a TCP/IP interface between first and second servers. The transaction logic has out-of-order segment range record stores and a protocol engine. The out-of-order segment range record stores maintains parameters associated with one or more out-of-order segments, the one or more out-of-order segments having been received and corresponding to one or more RDMA messages that are associated with the work queue elements. The protocol engine is coupled to the out-of-order segment range record stores and is configured to access the parameters to enable in-order completion tracking and reporting of the one or more RDMA messages.

Abstract: A mechanism for performing remote direct memory access (RDMA) operations between a first server and a second server. The apparatus includes a packet parser and a protocol engine. The packet parser processes a TCP segment within an arriving network frame, where the packet parser performs one or more speculative CRC checks according to an upper layer protocol (ULP), and where the one or more speculative CRC checks are performed concurrent with arrival of the network frame. The protocol engine is coupled to the packet parser. The protocol engine receives results of the one or more speculative CRC checks, and selectively employs the results for validation of a framed protocol data unit (FPDU) according to the ULP.

Abstract: A mechanism for performing remote direct memory access (RDMA) operations between a first server and a second server over an Ethernet fabric. The RDMA operations are initiated by execution of a verb according to a remote direct memory access protocol. The verb is executed by a CPU on the first server. The apparatus includes transaction logic that is configured to process a work queue element corresponding to the verb, and that is configured to accomplish the RDMA operations over a TCP/IP interface between the first and second servers, where the work queue element resides within first host memory corresponding to the first server. The transaction logic includes transmit history information stores and a protocol engine. The transmit history information stores maintains parameters associated with said work queue element.