Abstract: A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria.

Abstract: A computer system includes a processor, and the processor includes at least one interface for communicating with an electronic component. Each of the at least one interface has a set of interface settings. The computer system further includes a memory containing machine executable instructions. Execution of the instructions causes the processor to: monitor communications traffic on the at least one interface; store, eye distribution data acquired during the monitoring of the communications traffic in a database; compare the eye distribution data to a set of predetermined criteria; and generate a set of updated interface settings if the eye distribution does not satisfy the set of predetermined criteria.

Abstract: A method of wiring a plurality of integrated circuits within a chip or between chips in one or more packages by adding cluster points to a net that includes a plurality of nodes to be interconnected. The interconnected nodes are designed to meet system requirements, commonly expressed by a set of wiring rules, include among others, physical, electrical and noise constraints. The method includes matching interconnection net attributes to wiring rule logical definitions, wherein the wiring rules include rule nodes and rule connections. The rule nodes define constraints for the pins, vias and cluster point structures. The rule connections define wiring constraints between the node structures to establish the net topology. The process described is based on net ordering and checking. The net ordering, which defines the pin-to-pin connections based on the wiring rule, is performed prior to chip or package wiring.

Abstract: Permutations of orders of elements such as electrical connection pins, vias and t-junctions at known locations are efficiently tested against at least type and distance criteria by forming a plurality of lists of the elements and screening the elements of each list against respective ones of said type criteria to reduce the length of the lists of elements. Pointers to ones of the distance criteria and remaining members of a list corresponding to respective ones of the distance criteria iteratively form pairs of elements which are checked for separation. When the check fails or a solution is found, the pointer to list members is advanced. The pointer to respective distance criteria is advanced when a check is successful. When a list is exhausted and a check is unsuccessful, the pointer to respective distance criteria is regressed. Advancement and regression of pointers reduces iterations of combinations of pairs of elements which do not lead to a solution in order to accelerate the process.