Patents by Inventor Kenneth L. DeVries

Kenneth L. DeVries has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7759173
    Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.
    Type: Grant
    Filed: April 15, 2008
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: Kenneth L. DeVries, Nancy Anne Greco, Joan Preston, Stephen Larry Runyon
  • Publication number: 20080191309
    Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.
    Type: Application
    Filed: April 15, 2008
    Publication date: August 14, 2008
    Inventors: Kenneth L. DeVries, Nancy Anne Greco, Joan Preston, Stephen Larry Runyon
  • Patent number: 7408206
    Abstract: Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: August 5, 2008
    Assignee: International Business Machines Corporation
    Inventors: Kenneth L. DeVries, Nancy Anne Greco, Joan Preston, Stephen Larry Runyon
  • Patent number: 5431772
    Abstract: A two step method of etching a silicon nitride layer carrying a surface oxygen film from a substrate in a plasma reactor employs the steps of (1) a breakthrough step of employing a plasma of oxygen free etchant gases to break through and to remove the surface oxygen containing film from the surface of the silicon nitride layer, and (2) a main step of etching the newly exposed silicon nitride with etchant gases having high selectivity with respect to the silicon oxide underlying the silicon nitride. The plasma etching can be performed while employing magnetic- enhancement of the etching. The plasma etching is performed in a plasma reactor comprising a low pressure, single wafer tool. Plasma etching is performed while employing magnetic-enhancement of the etching. The etchant gases include a halide such as a bromide and a fluoride in the breakthrough step. The etchant gases include an oxygen and bromine containing gas in the main step.
    Type: Grant
    Filed: October 19, 1992
    Date of Patent: July 11, 1995
    Assignee: International Business Machines Corporation
    Inventors: Wayne T. Babie, Kenneth L. Devries, Bang C. Nguyen, Chau-Hwa J. Yang
  • Patent number: 5188704
    Abstract: A two step method of etching a silicon nitride layer carrying a surface oxygen film from a substrate in a plasma reactor employs the steps of (1) a breakthrough step of employing a plasma of oxygen free etchant gases to break through and to remove the surface oxygen containing film from the surface of the silicon nitride layer, and (2) a main step of etching the newly exposed silicon nitride with etchant gases having high selectivity with respect to the silicon oxide underlying the silicon nitride. The plasma etching can be performed while employing magnetic-enhancement of the etching. The plasma etching is performed in a plasma reactor comprising a low pressure, single wafer tool. Plasma etching is performed while employing magnetic-enhancement of the etching. The etchant gases include a halide such as a bromide and a fluoride in the breakthrough step. The etchant gases include an oxygen and bromine containing gas in the main step.
    Type: Grant
    Filed: May 9, 1991
    Date of Patent: February 23, 1993
    Assignee: International Business Machines Corporation
    Inventors: Wayne T. Babie, Kenneth L. Devries, Bang C. Nguyen, Chau-Hwa J. Yang