Patents by Inventor Kenneth P. Fuchs
Kenneth P. Fuchs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7176082Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.Type: GrantFiled: October 6, 2004Date of Patent: February 13, 2007Assignee: LSI Logic CorporationInventors: Todd A. Randazzo, Kenneth P. Fuchs, John de Q. Walker
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Patent number: 6822282Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.Type: GrantFiled: April 8, 2003Date of Patent: November 23, 2004Assignee: LSI Logic CorporationInventors: Todd A. Randazzo, Kenneth P. Fuchs, John de Q. Walker
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Publication number: 20030176035Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.Type: ApplicationFiled: April 8, 2003Publication date: September 18, 2003Applicant: LSI Logic CorporationInventors: Todd A. Randazzo, Kenneth P. Fuchs, John de Q. Walker
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Patent number: 6596579Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.Type: GrantFiled: April 27, 2001Date of Patent: July 22, 2003Assignee: LSI Logic CorporationInventors: Todd A. Randazzo, Kenneth P. Fuchs, John de Q. Walker
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Patent number: 6522005Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.Type: GrantFiled: July 18, 2000Date of Patent: February 18, 2003Assignee: Hyundai Electronics America Inc.Inventors: Derryl D. J. Allman, Kenneth P. Fuchs, Gayle W. Miller, Samuel C. Gioia
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Patent number: 6522006Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.Type: GrantFiled: October 23, 2000Date of Patent: February 18, 2003Assignee: Hyundai Electronics America Inc.Inventors: Derryl D. J. Allman, Kenneth P. Fuchs, Gayle W. Miller, Samuel C. Gioia
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Patent number: 6504250Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.Type: GrantFiled: October 23, 2000Date of Patent: January 7, 2003Assignee: Hyundai Electronics America Inc.Inventors: Derryl D. J. Allman, Kenneth P. Fuchs, Gayle W. Miller, Samuel C. Gioia
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Patent number: 6504249Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.Type: GrantFiled: April 26, 2000Date of Patent: January 7, 2003Assignee: Hyundai Electronics America Inc.Inventors: Derryl D. J. Allman, Kenneth P. Fuchs, Gayle W. Miller, Samuel C. Gioia
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Patent number: 6448653Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.Type: GrantFiled: October 23, 2000Date of Patent: September 10, 2002Inventors: Derryl D. J. Allman, Kenneth P. Fuchs, Gayle W. Miller, Samuel C. Gioia
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Patent number: 6358837Abstract: A vertically oriented metal circuit element is electrically connected and isolated between vertically separated conductors of interconnect layers in an integrated circuit. The methodology involves connecting a lower end of the metal element to the lower interconnect layer at the lower end of an opening in an inter-layer dielectric, preferably by simultaneously forming the metal element and connecting it to the conductor by vapor deposition. An upper end of the metal element initially extends above an upper surface of the inter-layer dielectric, and chemical mechanical polishing is employed to reduce the upper end to a level flush with the upper surface of the inter-layer dielectric. The flush upper end of the metal element allows it to be precisely spaced and covered with dielectric material to obtain predictable and reliable electrical isolation characteristics.Type: GrantFiled: March 31, 1998Date of Patent: March 19, 2002Assignee: LSI Logic CorporationInventors: Gayle W. Miller, Kenneth P. Fuchs
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Patent number: 6208029Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.Type: GrantFiled: March 31, 1997Date of Patent: March 27, 2001Assignee: Hyundai Electronics AmericaInventors: Derryl D. J. Allman, Kenneth P. Fuchs, Gayle W. Miller, Samuel C. Gioia
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Patent number: 6071817Abstract: The present invention applies a silicon nitride or the like as a mask over portions of a substrate, such as an active region, where oxide growth is undesired. Thereafter, without the formation of a recess in the substrate, a high pressure oxidation process is used to grow an oxide, preferably in a furnace. The oxide thus grows into the non-masked areas of the substrate, as well as over the silicon nitride used as a mask. Thereafter, a chemical-mechanical polish is used to etch away undesired oxide, with the silicon nitride being used as an endpoint to terminate the polish operation.Type: GrantFiled: March 23, 1998Date of Patent: June 6, 2000Assignee: LSI Logic CorporationInventors: Derryl D. J. Allman, Kenneth P. Fuchs
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Patent number: 6057571Abstract: A linear capacitor formed in an IC which has horizontally oriented interconnect layers that are vertically separated by dielectric material. Two separated metal plates of the capacitor are electrically connected to the conductors of different vertically-separated metal interconnect layers. The metal plates extend substantially vertically through the thicker dielectric material separating the interconnect layers, to provide a relatively high capacitance per unit of surface consumed. The interconnect layers to which the plates are connected are separated from a substrate of the IC by at least one layer of dielectric, to reduce parasitic effects. Forming the capacitor plates and the interconnect layers from at least some of the same metals simplifies construction and reduces cost, while providing linear response characteristics. Placing the capacitor between the interconnect layers avoids consuming space on the substrate to construct the capacitor.Type: GrantFiled: March 31, 1998Date of Patent: May 2, 2000Assignee: LSI Logic CorporationInventors: Gayle W. Miller, Kenneth P. Fuchs
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Patent number: 6010963Abstract: A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.Type: GrantFiled: December 5, 1995Date of Patent: January 4, 2000Assignee: Hyundai Electronics AmericaInventors: Derryl D. J. Allman, Kenneth P. Fuchs
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Patent number: 5543361Abstract: A process for forming a titanium silicide local interconnect between electrodes separated by a dielectric insulator on an integrated circuit. A first layer of titanium is formed on the insulator, and a layer of silicon is formed on the titanium. The silicon layer is masked and etched to form a silicon strip connecting the electrodes, and an overlying second layer of titanium is formed over the silicon strip. The titanium and silicon are heated to form nonsilicidized titanium over a strip of titanium silicide, and the nonsilicidized titanium is removed.Type: GrantFiled: December 8, 1994Date of Patent: August 6, 1996Assignees: AT&T Global Information Solutions Company, Hyundai Electronics America, Symbios Logic Inc.Inventors: Steven S. Lee, Kenneth P. Fuchs, Gayle W. Miller
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Patent number: 5447880Abstract: A method for forming an amorphous silicon programable element which requires less than about one square micron of area. The method includes the steps of forming a bottom conductor, depositing an interlayer dielectric above the bottom conductor, forming a via in the interlayer dielectric, depositing an anti-fuse layer above the bottom conductor within the via, and chemical vapor depositing a conductive plug above the anti-fuse layer and within the via. The method may additionally include the step of chemical vapor depositing a top conductor above the conductive plug.Type: GrantFiled: April 5, 1994Date of Patent: September 5, 1995Assignees: AT&T Global Information Solutions Company, Hyundai Electronics AmericaInventors: Steven S. Lee, Kenneth P. Fuchs, Gayle W. Miller
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Patent number: 5443996Abstract: A process for forming a titanium silicide local interconnect between electrodes separated by a dielectric insulator on an integrated circuit. A first layer of titanium is formed on the insulator, and a layer of silicon is formed on the titanium. The silicon layer is masked and etched to form a silicon strip connecting the electrodes, and an overlying second layer of titanium is formed over the silicon strip. The titanium and silicon are heated to form nonsilicidized titanium over a strip of titanium silicide, and the nonsilicidized titanium is removed.Type: GrantFiled: May 14, 1990Date of Patent: August 22, 1995Assignees: AT&T Global Information Solutions Company, Hyundai Electronics AmericaInventors: Steven S. Lee, Kenneth P. Fuchs, Gayle W. Miller
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Patent number: 5438022Abstract: A low dielectric material is applied, as by spinning on, over the passivation layer of a semiconductor chip to fill the gaps which may exist between the top layer metal lines, and thereby minimize the possibility of cross talk which might otherwise be present between those lines.Type: GrantFiled: December 14, 1993Date of Patent: August 1, 1995Assignees: AT&T Global Information Solutions Company, Hyundai Electronics AmericaInventors: Derryl D. J. Allman, Kenneth P. Fuchs, Gayle W. Miller, Samuel C. Gioia
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Patent number: 5312512Abstract: A method for planarizing the surface of a semiconductor device which employs spin on glass (SOG) and an etching operation to remove high portions of the SOG prior to a chemical metal polish (CMP) operation. The SOG is baked and cured before etching. Additional layers of SOG and etching operations may be employed as necessary. A thick encapsulating oxide layer is deposited over the SOG layer. For surface irregularities caused by metal lines, an insulating layer may be deposited over the surface before the SOG. Where an additional metal line is to be deposited on the surface, an additional insulating layer is deposited after the CMP operation. In the case of metal lines made of aluminum, provision is also made for preventing Hillock formations on the metal lines.Type: GrantFiled: October 23, 1992Date of Patent: May 17, 1994Assignee: NCR CorporationInventors: Derryl D. J. Allman, Kenneth P. Fuchs