Patents by Inventor Kenneth Rovers
Kenneth Rovers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11961175Abstract: A method of performing anisotropic texture filtering includes generating one or more parameters describing an elliptical footprint in texture space; performing isotropic filtering at each of a plurality of sampling points along a major axis of the elliptical footprint, wherein a spacing between adjacent sampling points of the plurality of sampling points is proportional to ?{square root over (1???2)} units, wherein ? is a ratio of a major radius of an ellipse to be sampled and a minor radius of the ellipse to be sampled, wherein the ellipse to be sampled is based on the elliptical footprint; and combining results of the isotropic filtering at the plurality of sampling points with a Gaussian filter to generate at least a portion of a filter result.Type: GrantFiled: July 26, 2022Date of Patent: April 16, 2024Assignee: Imagination Technologies LimitedInventors: Rostam King, Kenneth Rovers
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Publication number: 20240095975Abstract: A decoder decodes a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format. A parameter decode unit decodes configuration data for the received block of texture data, a colour decode unit decodes colour endpoint data for the plurality of texels in dependence on the configuration data, a weight decode unit decodes interpolation weight data for each of the plurality of texels in dependence on the configuration data, and at least one interpolator unit calculates a colour value for each of the plurality of texels using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data. At least one of the parameter decode unit, colour decode unit and weight decode unit decodes intermediate data from the received block that is common to the decoding of a subset of texels of that block and uses that decoded data as part of the decoding of at least two of the plurality of texels.Type: ApplicationFiled: November 30, 2023Publication date: March 21, 2024Inventors: Kenneth Rovers, Yoong Chert Foo
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Publication number: 20230409287Abstract: Accumulator hardware logic includes first and second addition logic units and a store. The first addition logic unit comprises a first input, a second input and an output, each of the first and second inputs arranged to receive an input value in each clock cycle. The second addition logic unit comprises a first input that is connected directly to the output of the first addition logic unit. It also comprises a second input and an output. The store is arranged to store a result output by the second addition logic unit. The accumulator hardware logic further comprises shifting hardware and/or negation hardware positioned in a feedback path between the store and the second input of the second addition logic unit. The shifting hardware is configured to perform a shift by a fixed number of bit positions in a fixed direction.Type: ApplicationFiled: March 30, 2023Publication date: December 21, 2023Inventors: Kenneth Rovers, Faizan Nazar
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Publication number: 20230401762Abstract: A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) low-dynamic range (LDR) colour endpoint values C0 and C1 respectively, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; and combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation P=?((C2<<8)+C2+32)/64? when the interpolated result is not to be compatible with an sRGB colour space, and according to the equation P=?((C2<<8)+128·64+32)/64? when the interpolated result is to be compatible with an sRGB colour space.Type: ApplicationFiled: August 29, 2023Publication date: December 14, 2023Inventor: Kenneth Rovers
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Publication number: 20230394626Abstract: A binary logic circuit performs an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) colour endpoint values C0 and C1 respectively, the colour endpoint values C0 and C1 being low-dynamic range (LDR) or high dynamic range (HDR) values.Type: ApplicationFiled: August 21, 2023Publication date: December 7, 2023Inventor: Kenneth Rovers
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Patent number: 11836830Abstract: A decoder is configured to decode a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format, and includes a parameter decode unit configured to decode configuration data for the received block of texture data, a colour decode unit configured to decode colour endpoint data for the plurality of texels of the received block in dependence on the configuration data, a weight decode unit configured to decode interpolation weight data for each of the plurality of texels of the received block in dependence on the configuration data, and at least one interpolator unit configured to calculate a colour value for each of the plurality of texels of the received block using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data.Type: GrantFiled: January 25, 2023Date of Patent: December 5, 2023Assignee: Imagination Technologies LimitedInventors: Kenneth Rovers, Yoong Chert Foo
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Publication number: 20230384374Abstract: An error detection circuit and a method for performing a cyclic redundancy check on a clock gated register signal are disclosed. The error detection circuit comprising a first register, a check bit processing logic and an error detection module. The first register is a clock gated register configured to be updated with a data signal (x) in response to a clock enabling signal. The check bit processing logic configured to, in response to a control signal, update a second register with a check bit, wherein the control signal (b) is the same as the clock enabling signal. The error detection module configured for calculating an indication bit based on at least the output of the first register and the output of the second register.Type: ApplicationFiled: March 30, 2023Publication date: November 30, 2023Inventors: Faizan Nazar, Kenneth Rovers
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Publication number: 20230384375Abstract: An error detection circuit and method for performing cyclic redundancy check on a clock gated register signal is disclosed. The error detection circuit comprise a first register, a second register, a third register and an error detection module. The first register is a clock gated register and is configured to be updated with a data signal (x) in response to a clock enabling signal. The second register is configured to be updated with a check bit (c) based on the data signal (x). The check bit is calculated by a check bit calculation unit. The third register is configured to be updated with a current value (b) of the clock enabling signal. The error detection module is configured for calculating an indication bit (I) based on at least the output of the first register, the output of the second register and the output of the third register.Type: ApplicationFiled: March 30, 2023Publication date: November 30, 2023Inventors: Faizan Nazar, Kenneth Rovers
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Patent number: 11741641Abstract: A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) low-dynamic range (LDR) colour endpoint values C0 and C1 respectively, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; and combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation P=?((C2<<8)+C2+32)/64? when the interpolated result is not to be compatible with an sRGB colour space, and according to the equation P=?((C2<<8)+128·64+32)/64? when the interpolated result is to be compatible with an sRGB colour space.Type: GrantFiled: March 2, 2022Date of Patent: August 29, 2023Assignee: Imagination Technologies LimitedInventor: Kenneth Rovers
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Patent number: 11734794Abstract: A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) colour endpoint values C0 and C1 respectively, the colour endpoint values C0 and C1 being low-dynamic range (LDR) or high dynamic range (HDR) values, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation: (1) P=?(C2<<8)+C2+32)/64? when the interpolated result is not to be compatible with an sRGB colour space and the colour endpoint values are LDR values; (2) P=?(C2<<8)+128.Type: GrantFiled: July 30, 2021Date of Patent: August 22, 2023Assignee: Imagination Technologies LimitedInventor: Kenneth Rovers
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Publication number: 20230176814Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B = 2ew-1 - 1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew - 1), bitwidth(iw - 2 - sy)} ? k ? (ew - 1) where sy = 1 for a signed floating point number and sy = 0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.Type: ApplicationFiled: February 1, 2023Publication date: June 8, 2023Inventor: Kenneth Rovers
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Publication number: 20230169701Abstract: A decoder is configured to decode a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format, and includes a parameter decode unit configured to decode configuration data for the received block of texture data, a colour decode unit configured to decode colour endpoint data for the plurality of texels of the received block in dependence on the configuration data, a weight decode unit configured to decode interpolation weight data for each of the plurality of texels of the received block in dependence on the configuration data, and at least one interpolator unit configured to calculate a colour value for each of the plurality of texels of the received block using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data.Type: ApplicationFiled: January 25, 2023Publication date: June 1, 2023Inventors: Kenneth Rovers, Yoong Chert Foo
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Publication number: 20230146982Abstract: A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2ew-1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits.Type: ApplicationFiled: January 4, 2023Publication date: May 11, 2023Inventor: Kenneth Rovers
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Publication number: 20230055989Abstract: A method of performing anisotropic texture filtering includes generating one or more parameters describing an elliptical footprint in texture space; performing isotropic filtering at each of a plurality of sampling points along a major axis of the elliptical footprint, wherein a spacing between adjacent sampling points of the plurality of sampling points is proportional to ?{square root over (1???2)} units, wherein ? is a ratio of a major radius of an ellipse to be sampled and a minor radius of the ellipse to be sampled, wherein the ellipse to be sampled is based on the elliptical footprint; and combining results of the isotropic filtering at the plurality of sampling points with a Gaussian filter to generate at least a portion of a filter result.Type: ApplicationFiled: July 26, 2022Publication date: February 23, 2023Inventors: Rostam King, Kenneth Rovers
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Patent number: 11588497Abstract: A binary logic circuit converts a number in floating point format having an exponent E, an exponent bias B=2ew-1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits.Type: GrantFiled: December 31, 2020Date of Patent: February 21, 2023Assignee: Imagination Technologies LimitedInventor: Kenneth Rovers
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Patent number: 11573766Abstract: A binary logic circuit converts a number in floating point format having an exponent E of ew bits, an exponent bias B given by B=2ew-1?1, and a significand comprising a mantissa M of mw bits into a fixed point format with an integer width of iw bits and a fractional width of fw bits. The circuit includes a shifter operable to receive a significand input comprising a contiguous set of the most significant bits of the significand and configured to left-shift the significand input by a number of bits equal to the value represented by k least significant bits of the exponent to generate a shifter output, wherein min{(ew?1),bitwidth(iw?2?sy)}?k?(ew?1) where sy=1 for a signed floating point number and sy=0 for an unsigned floating point number, and a multiplexer coupled to the shifter and configured to: receive an input comprising a contiguous set of bits of the shifter output; and output the input if the most significant bit of the exponent is equal to one.Type: GrantFiled: January 5, 2021Date of Patent: February 7, 2023Assignee: Imagination Technologies LimitedInventor: Kenneth Rovers
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Patent number: 11568580Abstract: A decoder is configured to decode a plurality of texels from a received block of texture data encoded according to the Adaptive Scalable Texture Compression (ASTC) format, and includes a parameter decode unit configured to decode configuration data for the received block of texture data, a colour decode unit configured to decode colour endpoint data for the plurality of texels of the received block in dependence on the configuration data, a weight decode unit configured to decode interpolation weight data for each of the plurality of texels of the received block in dependence on the configuration data, and at least one interpolator unit configured to calculate a colour value for each of the plurality of texels of the received block using the interpolation weight data for that texel and a pair of colour endpoints from the colour endpoint data.Type: GrantFiled: January 28, 2021Date of Patent: January 31, 2023Assignee: Imagination Technologies LimitedInventors: Kenneth Rovers, Yoong Chert Foo
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Patent number: 11544892Abstract: A decoder unit is configured to decode a plurality of texels in accordance with a texel request, the plurality of texels being encoded across one or more blocks of encoded texture data each encoding a block of texels, and includes a first set of one or more decoders, each of the first set of decoders being configured to decode n texels from a single received block of encoded texture data; a second set of or more decoders, each of the second set of decoders being configured to decode p texels from a single received block of encoded texture data, where p<n; and control logic configured to allocate blocks of encoded texture data to the decoders in accordance with the texel request.Type: GrantFiled: June 8, 2021Date of Patent: January 3, 2023Assignee: Imagination Technologies LimitedInventors: Yoong Chert Foo, Kenneth Rovers
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Publication number: 20220414951Abstract: A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) low-dynamic range (LDR) colour endpoint values C0 and C1 respectively, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; and combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation P=?((C2<<8)+C2+32)/64? when the interpolated result is not to be compatible with an sRGB colour space, and according to the equation P=?((C2<<8)+128.64+32)/64? when the interpolated result is to be compatible with an sRGB colour space.Type: ApplicationFiled: March 2, 2022Publication date: December 29, 2022Inventor: Kenneth Rovers
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Patent number: 11295485Abstract: A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) low-dynamic range (LDR) colour endpoint values C0 and C1 respectively, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; and combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation P=?((C2<<8)+C2+32)/64? when the interpolated result is not to be compatible with an sRGB colour space, and according to the equation P=?((C2<<8)+128.64+32)/64? when the interpolated result is to be compatible with an sRGB colour space.Type: GrantFiled: December 20, 2019Date of Patent: April 5, 2022Assignee: Imagination Technologies LimitedInventor: Kenneth Rovers