Abstract: Wavelength-selective films are visibly apparent under the selective wavelength. Wavelength-selective films typically reflect off axis the selected wavelength and therefore can provide high-contrast against a background when applied in a pattern on a substrate. However, it is difficult to apply unique patterned embedded images from film. Disclosed is a cost-effective method and construction of a patterned wavelength-selective image to a substrate. In the disclosed wavelength-selective image, wavelength-selective film particles are applied to an adhesive pattern to create the wavelength-selective image.

Abstract: A clock frequency mode switching system for a microprocessor comprising three frequency shifters, a phase-locked loop (PLL) circuit, a synchronizer, and a comparator. To switch frequency modes, a CPU provides a command signal to at least one of the frequency shifter circuits to change its frequency division ratio. The signal is detected by the comparator which compares the current frequency division ratio of each of the frequency shifters to the CPU frequency command signal for each frequency shifter. The comparator outputs a reload signal to the synchronizer circuit. The synchronizer circuit aligns the reload signal to the PLL output signal and selects the appropriate PLL circuit output cycles that the division ratio of each of the frequency shifters should be updated on. To maintain phase-lock the third frequency shifter division ratio is updated first.

Abstract: An integrated processor includes a microprocessor core and a bus interface unit. The integrated processor receives a reference clock signal and an external clock signal. The frequency of the reference clock signal is compared to the frequency of the external clock signal. Based upon this comparison, the appropriate frequency for the internal clock signal that controls the bus interface unit is determined. A clock generation circuit, such as a phase-locked loop, generates the appropriate frequency for the internal clock signal based upon the comparison of the reference clock signal and external clock signal.

Abstract: Method and apparatus for controlling a PLL so that handover between fine and coarse loops take place at 2.5% of the nominal VCO frequency and where the coarse and fine loops error are combined in a summer circuit which employs a series circuit having a P-channel and N-channel FET with common drains and where the drains connected to the summer output node.