Abstract: An improved radar signature evaluation apparatus for measuring and evaluating the radar signature for an aircraft, missiles, and other vehicle. The radar signature apparatus includes an instrumentation system for generating radar cross section data for the vehicle being evaluated and a computer for processing the radar cross section data and a printer for printing various plots derived from the radar cross section data.

Abstract: An aqueous thiourea-ammonia treatment is used to form a thin sulfurous film at the indium phosphide surface, having a thickness of less than one nanometer. The thiourea-ammonium hydroxide treatment can be used as is or immediately prior to deposition of cadmium sulfide for enhanced surface passivation. The thiourea-ammonium hydroxide treatment is entirely compatible with chemical bath deposition, molecular beam epitaxy, or metalorganic chemical vapor deposition of the cadmium sulfide.

Abstract: In an active radar augmentation system a microwave switch is connected been the receiving antenna and the amplifier. When there is an RF input signal to the receiving antenna of the augmentation system, a square wave timing signal provided to the microwave switch is adjusted to have the microwave switch in an open state during a time period when the coupling or feedback signal from the transmitting antenna of the augmentation system is received by the receiving antenna. The "on-off" timing of the square wave signal is set equal to the external time delay of the feedback signal plus the internal time delay of the RF signal as the RF signal passes through the augmentation system. Under this condition, the feedback signal coupled by antenna leakage arrives at the output of the receiving antenna while the microwave switch is in the open state.

Abstract: A novel indium phosphide (InP) based heterojunction bipolar transistor (HBT) is described. A II-VI compound, cadmium sulfide (CdS), is used as the emitter to improve the emitter injection efficiency and reduce recombination losses. The cadmium sulfide emitter is applied following the epitaxial growth of III-V compound collector and base regions. The large valence band discontinuity (.quadrature.E=0.75 eV) between CdS and InP allows InP to be used for both the base and collector material. Prior to cadmium sulfide deposition, the exposed surfaces of the epitaxial layers can be passivated with sulfur, further reducing the recombination losses.

Abstract: In a Schottky metal junction semiconductor device, a CdS interface layer, having a thickness of under 100 angstroms, is positioned under the Schottky barrier gate of a III-V HEMT, for reducing gate leakage, and for enabling full depletion of the conducting channel. A similar layer is positioned under the insulator of an MIS device having an InP substrate. The CdS layers are deposited from a chemical bath which merely entails a simple, safe and readily controllable additional step in the otherwise conventional manufacturing process of these devices.

Abstract: A vertical structure Schottky contact photodiode has a narrow bandgap InGaAs light absorbing layer cladded front and back with InAlAs current blocking layers having metal contacts formed thereon. As compared to single-side MSM photodiodes, with interdigitated electrodes lying in a single plane, response time is improved due to reduced spacing between the electrodes. Response time is also improved since capacitance is reduced due to inherently low doping levels in the semiconductor material. Laterally offset finger electrodes are made light reflective to increase the production of carriers in the InGaAs absorption layer.

Abstract: An InP buffer layer is first formed upon an InP substrate; a thin layer of heavily doped InGaAs, a thick layer of light absorbing InGaAs, and a thin layer of InAlAs are thereafter sequentially grown upon the InP buffer layer. A light reflective Schottky barrier metallic layer is then applied to the InAlAs layer and the resulting device is inverted and affixed to a newly provided substrate, to thus shield and protect the sensitive Schottky contact. The InP substrate layers are thereafter removed and the now exposed thin, heavily doped InGaAs layer is coated with a transparent, electrically conductive layer of Indium-tin-oxide.

Abstract: A system for functionally testing opto-electronic devices, such as fiber-optic infrared receiver photodiodes, in the integral wafer or other optical port-exposed status. The testing arrangement uses a portable optical probe for communicating optical signals between the testing apparatus and the tested device in coincidence with electrical energization and functional operation of the electro-optical device by the test apparatus. The optical probe signals may be correlated in time relationship or other manner with the electrical signals applied-to the device-under-test. The invention provides simple conversion between a conventional electrical semiconductor device probe station and an electro-optical device probe station.

Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration using a lattice determining surrogate substrate and a mesa-forming deep etch processing sequence and then inverted onto a new permanent substrate member and the surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Fabrication of the device from two possible indium-inclusive semiconductor materials and a particular gate metal alloy is also disclosed.

Abstract: A full wafer to full wafer integrated circuit apparatus wherein substrate removal and replacement on one wafer has been used to enable an accurate alignment of this wafer with features of a receiving wafer during a see through alignment step. The invention is disclosed in terms of a wafer of photo field effect transistors being combined with a wafer of circuit devices that attend the photo feed effect transistor devices. Use of the invention with the different material combination option desired for a photodetector device and its attending circuitry is also disclosed. Advantages over the more conventional chip by chip combination of wafer devices are also disclosed.

Abstract: An improved Metal Semiconductor Metal (MSM) photodiode device and a fabrication process for realizing this device. The improved photodiode device employs frontside electrodes and backside illumination to avoid active area shadowing in the device. This configuration is achieved through a device fabrication sequence which involves substrate removal--and replacement at the device's opposed frontside surface using such media as an epoxy adhesive. The disclosed device uses gallium arsenide semiconductor materials that are lattice determined by an indium phosphide sacrificial initial substrate, in order to select a desired input energy spectral range.

Abstract: A photo FET device having a large area backside optical energy reception surface is disclosed. The photo FET device is fabricated in the source gate and drain upward configuration using a lattice determining surrogate substrate and a mesa-forming deep etch processing sequence and then inverted onto a new permanent substrate member and the surrogate substrate member removed in order to expose the active area backside optical energy reception surface. Fabrication of the device from two possible indium-inclusive semiconductor materials and a particular gate metal alloy is also disclosed.

Abstract: An improved Metal Semiconductor Metal (MSM) photodiode device and a fabrication process for realizing this device. The improved photodiode device employs frontside electrodes and backside illumination to avoid active area shadowing in the device. This configuration is achieved through a device fabrication sequence which involves substrate removal--and replacement at the device's opposed frontside surface using such media as an epoxy adhesive. The disclosed device uses gallium arsenide semiconductor materials that are lattice determined by an indium phosphide sacrificial initial substrate, in order to select a desired input energy spectral range.

Abstract: A full wafer to full wafer integrated circuit fabrication process wherein substrate removal and replacement of one wafer is used to enable an accurate alignment of this wafer with features of a receiving wafer during a see through alignment step. The invention is disclosed in terms of a wafer of photo field effect transistors being combined with a wafer of circuit devices that attend the photo field effect transistor devices. Use of the invention with the different material combination option desired for a photodetector device and its attending circuitry is also disclosed. Advantages over the more conventional chip by chip combination of wafer devices are also disclosed.

Abstract: The invention comprises a pyrolytic process for the deposition of high quality silicon dioxide at temperatures of 100.degree.-330.degree. C. Deposition is achieved by reacting silane and oxygen in the 2-12 torr pressure range, yielding deposition rates of 140 .ANG./min at 300.degree. C. and 50 .ANG./min at 120.degree. C. Measurements of refractive index (1.45-1.46), field strength (3-10.times.10.sup.6 V/cm), and resistivity (10.sup.13 -10.sup.15 -cm) indicate that the oxides are near stoichiometric SiO.sub.2. This technology appears promising the Group IV and Group III-V device applications.