Abstract: A logic circuit for managing reception of secure data packets in an industrial controller snoops data being transferred by a Media Access Controller (MAC) between a network port and a shared memory location within the industrial controller. The logic circuit is configured to perform authentication and/or decryption on the data packet as the data packet is being transferred between the port and the shared memory location. The logic circuit performs authentication as the data is being transferred and completes authentication shortly after the MAC has completed transferring the data to the shared memory. The logic circuit coordinates operation with the MAC and signals a Software Packet Processing (SPP) module when authentication is complete. The logic circuit is further configured to decrypt the data packet, if necessary, and to similarly coordinate operation with the MAC and delay signaling the SPP module that data is ready until decryption is complete.

Abstract: A logic circuit for managing reception of secure data packets in an industrial controller snoops data being transferred by a Media Access Controller (MAC) between a network port and a shared memory location within the industrial controller. The logic circuit is configured to perform authentication and/or decryption on the data packet as the data packet is being transferred between the port and the shared memory location. The logic circuit performs authentication as the data is being transferred and completes authentication shortly after the MAC has completed transferring the data to the shared memory. The logic circuit coordinates operation with the MAC and signals a Software Packet Processing (SPP) module when authentication is complete. The logic circuit is further configured to decrypt the data packet, if necessary, and to similarly coordinate operation with the MAC and delay signaling the SPP module that data is ready until decryption is complete.

Abstract: A logic circuit for generation of data signatures and/or encryption of data packets to be transferred from an industrial controller snoops data as it is written to an output buffer within the industrial controller. The logic circuit generates a secure signature and/or coordinates encryption of the data packet being transferred between the shared memory location and the output buffer. If encryption of the data is required, an encryption module may both encrypt the data and generate a secure signature. If encryption is not required, the logic circuit generates the secure signature. In either case, the logic circuit controls ownership of the memory address in which the secure signature is to be written to coordinate with the MAC transferring the secure signature to the output buffer, providing a uniform interface between the SPP module and the MAC.

Abstract: A logic circuit for managing reception of secure data packets in an industrial controller snoops data being transferred by a Media Access Controller (MAC) between a network port and a shared memory location within the industrial controller. The logic circuit is configured to perform authentication and/or decryption on the data packet as the data packet is being transferred between the port and the shared memory location. The logic circuit performs authentication as the data is being transferred and completes authentication shortly after the MAC has completed transferring the data to the shared memory. The logic circuit coordinates operation with the MAC and signals a Software Packet Processing (SPP) module when authentication is complete. The logic circuit is further configured to decrypt the data packet, if necessary, and to similarly coordinate operation with the MAC and delay signaling the SPP module that data is ready until decryption is complete.

Abstract: A logic circuit for generation of data signatures and/or encryption of data packets to be transferred from an industrial controller snoops data as it is written to an output buffer within the industrial controller. The logic circuit generates a secure signature and/or coordinates encryption of the data packet being transferred between the shared memory location and the output buffer. If encryption of the data is required, an encryption module may both encrypt the data and generate a secure signature. If encryption is not required, the logic circuit generates the secure signature. In either case, the logic circuit controls ownership of the memory address in which the secure signature is to be written to coordinate with the MAC transferring the secure signature to the output buffer, providing a uniform interface between the SPP module and the MAC.

Abstract: A dual cryptographic keying system. In particular implementations, a method includes responsive to an initial session key negotiation, storing security association information for a tunnel in a security association memory; responsive to a session key renegotiation, storing security association information for the tunnel in a cache; decrypting received packets associated with the tunnel conditionally using the security association information in the cache or the security association information in the security association memory; and upon an expiration condition, overwriting the security association information, for the tunnel, in the security association memory with the security association information, for the tunnel, copied from the cache.

Abstract: A dual cryptographic keying system. In particular implementations, a method includes responsive to an initial session key negotiation, storing security association information for a tunnel in a security association memory; responsive to a session key renegotiation, storing security association information for the tunnel in a cache; decrypting received packets associated with the tunnel conditionally using the security association information in the cache or the security association information in the security association memory; and upon an expiration condition, overwriting the security association information, for the tunnel, in the security association memory with the security association information, for the tunnel, copied from the cache.

Abstract: A dual cryptographic keying system. In particular implementations, a method includes responsive to an initial session key negotiation, storing security association information for a tunnel in a security association memory; responsive to a session key renegotiation, storing security association information for the tunnel in a cache; decrypting received packets associated with the tunnel conditionally using the security association information in the cache or the security association information in the security association memory; and upon an expiration condition, overwriting the security association information, for the tunnel, in the security association memory with the security association information, for the tunnel, copied from the cache.

Abstract: A dual cryptographic keying system. In particular implementations, a method includes responsive to an initial session key negotiation, storing security association information for a tunnel in a security association memory; responsive to a session key renegotiation, storing security association information for the tunnel in a cache; decrypting received packets associated with the tunnel conditionally using the security association information in the cache or the security association information in the security association memory; and upon an expiration condition, overwriting the security association information, for the tunnel, in the security association memory with the security association information, for the tunnel, copied from the cache.

Abstract: A method and apparatus for testing a digital integrated circuit (IC) for faults wherein the IC includes a memory, a microprocessor, an operand register, and a random data generator which is responsive to integrated circuit data indicative of the instantaneous IC state. A short test code including operational code instructions in the memory is performed by the microprocessor which manipulates data in the operand register. Periodically, the random data generator provides seed data to the microprocessor which changes the test code in a random manner and modifies the data stored in the operand register. At the end of a prescribed number of passes through the test code, the data generator produces an IC signature which can be compared to a known correct signature to identify IC faults.