Abstract: The invention relates to a hybrid network device comprising a server interface enabling access to a server system memory, a network switch comprising a packet processing engine configured to process packets routed through the switch and a switch packet buffer configured to queue packets before transmission, at least one network interface; and at least one a bus mastering DMA controller configured to access the data of said server system memory via said at least one server interface and transfer said data to and from said hybrid network device. According to one aspect of the invention, a bus transfer arbiter configured to control the data transfer from the server memory to the packet processing engine of said hybrid network device.

Abstract: The present invention relates to a computer chip having integrated thereon a CPU, and a cache system being interconnected, and at least one synchronization unit. The chip is setable in one of at least two different running modes, a first one thereof being a DUT mode, and a second one thereof being a MONITOR mode. The MONITOR mode is complementary to the DUT mode. The chip additionally comprises a debug bus connectable to another identical chip for communicating signals enabling the chip and said another chip to run in parallel while said chips being in complementary modes. Said signals comprises synchronization signals generated by said synchronization unit. The present invention further relates to a computer apparatus, and a debugging system both employing at least one such chip.

Abstract: The present invention relates to an application specific integrated circuit (ASIC) comprising an integrated central processor unit (CPU) (10), an integrated network interface control (NIC) (11) and at least one integrated input/output (I/O) device (13-16), and a transceiver circuit for buffering and amplifying SCSI signals from such an ASIC, whereby the outputs can be enabled to function as totem-pole or open-drain outputs, for active negation and wired-OR, respectively. According to the invention at least one I/O device is an ATA (16) or SCSI (15) device, with ports for connection to an external transceiver. The invention also relates to such a transceiver circuit for buffering and amplifying SCSI signals on single direction lines from an ASIC, whereby the outputs to the SCSI bus can be enabled to function as totem-pole or open-drain outputs, for active negation and wired-OR, respectively.

Abstract: An integrated circuit comprises a CPU, ports for external communication, a memory means and a switching means for converting the circuit between a working mode and an initiating mode. The circuit is in itself, in the initiating mode, adapted to receive an initiating signal, comprising external instructions, and to bring the CPU to execute said instructions.

Abstract: An integrated circuit comprises a CPU, ports for external communication, a memory means and a switching means for converting the circuit between a working mode and an initiating mode. The circuit is in itself, in the initiating mode, adapted to receive an initiating signal, comprising external instructions, and to bring the CPU to execute said instructions. According to a method for bringing the integrated circuit to execute instructions, the integrated circuit is in a first step brought into the initiating mode. Thereafter the circuit receives said external signal and uses the integrated CPU to execute said instructions.

Abstract: An on-chip i/o-processor for controlling and communication with peripheral devices, wherein an i/o processor core (12), comprising at least one pin controller (29) for reading and setting physical i/o-pins (6), starting timers and generating interrupts for the i/o processor core (12), at least one timer (26) for sampling i/o-pins (6), setting i/o-pins (6) and generating interrupts for the i/o-processor core (12) at well defined points of time, said i/o-processor core (12) providing instructions for controlling said at least one pin controller (29), said at least one timer (26) and i/o-pins (6), an on chip RAM (3) holding instructions for the i/o processor core (12), at least one register (4) for exchanging information between the i/o-processor (2) and a connected CPU (1) on the same chip and inversely, configurable logic (5), connected between said core (12) and said i/o-pins (6), for synchronization of incoming and/or outgoing signals.