Abstract: A non-volatile memory device including a plurality of block, each including: a main bit line; a plurality of sub-bit lines to which memory transistors are connected and which are arranged in parallel with respect to the main bit line; and two cascade-connected selection gates which are provided between the main bit line and sub-bit lines and which selectively connect the sub-bit lines.

Abstract: A semiconductor nonvolatile memory device wherein memory transistors in which data is electrically programmed in units of pages by performing the data programming together for selected memory transistors of a sector selected in response to page program data in units of sectors are arranged in the form of a matrix, provided with a means for continuously inputting the page program data of a plurality of page areas in synchronization with a constant clock pulse and continuously performing the page programming according to the plurality of page program data.

Abstract: A semiconductor nonvolatile memory device where the source line is selected and the channel portions of NAND strings adjacent in the row direction are charged up to the programming prohibit potential, the programming prohibit potential charged in the channel portion of the NAND strings is discharged to the bit lines according to the content of data to be programmed, and then the programming voltage is supplied to the selected word line and page programming is carried out together for memory transistors connected to the selected word lines. By this, the memory is suited for operation by a single power supply at a low voltage, enables easy layout of the data latch circuits for every bit line, and in addition performs a data programming operation with a good disturb tolerance.

Abstract: A semiconductor nonvolatile memory wherein memory cells in which data is electrically processed are arranged in the form of a matrix, provided with an error correcting circuit for correcting error bits when there are less than a predetermined number of error bits in a plurality of bits of data; a circuit for processing data in units of the plurality of bits of data in the memory cells of the plurality of units and for counting the number of the unprocessed memory cells after data is processed; and a circuit for ending the processing of the data while leaving the unprocessed memory cells when the number of the unprocessed memory cells is less than the predetermined number of error bits and making the error correcting means save the error bits.

Abstract: A semiconductor nonvolatile memory wherein memory cells in which data is electrically processed are arranged in the form of a matrix, provided with an error correcting circuit for correcting error bits when there are less than a predetermined number of error bits in a plurality of bits of data; a circuit for processing data in units of the plurality of bits of data in the memory cells of the plurality of units and for counting the number of the unprocessed memory cells after data is processed; and a circuit for ending the processing of the data while leaving the unprocessed memory cells when the number of the unprocessed memory cells is less than the predetermined number of error bits and making the error correcting means save the error bits.

Abstract: A semiconductor nonvolatile memory device where a main bit line is divided into a plurality of sub bit lines via operational connecting means, memory transistors connected to the sub bit lines are arranged in the form of a matrix, and control gate electrodes of these memory transistors are connected to word lines, provided with a means for setting sub bit lines at a programming prohibit potential at the time of a data programming operation; a means for causing a discharge in a selected sub bit line among the sub bit lines set to the programming prohibit potential and placing the non-selected sub bit lines among the sub bit lines in a floating state; and a means for supplying a program voltage to the selected word line.

Abstract: A semiconductor nonvolatile memory wherein memory cells in which data is electrically processed are arranged in the form of a matrix, provided with an error correcting circuit for correcting error bits when there are less than a predetermined number of error bits in a plurality of bits of data; a circuit for processing data in units of the plurality of bits of data in the memory cells of the plurality of units and for counting the number of the unprocessed memory cells after data is processed; and a circuit for ending the processing of the data while leaving the unprocessed memory cells when the number of the unprocessed memory cells is less than the predetermined number of error bits and making the error correcting means save the error bits.

Abstract: In a flash type EEPROM device, when a dose amount of an impurity of a floating gate is controlled, or, a channel of a transistor is buried by an ion implantation, the threshold value at no charges accumulated is set between the threshold at writing and the threshold at erasure, to reduce the disturbances of a drain and a gate when reading.

Abstract: A semiconductor nonvolatile memory device enabling high speed, high precision data programming and have a large disturb margin, that is, a NAND type flash memory wherein the programming operation is performed by repeating a programming operation a plurality of times through a verify read operation, where the programming word line voltages VPP1 to VPPk and an intermediate prohibit voltage VM1 to Vmk are set to values which are incremented along with an increase of the number k of programming and where the voltage increments of the intermediate prohibit voltage for each increase of the number of programming is set to half of the voltage increments of the programming word line voltage for each increase of the number of programming. Due to this, high speed, high precision data programming becomes possible and further the degradation of the disturb margin can be eliminated.

Abstract: A semiconductor memory wherein memory cells are arranged in a matrix and word lines or bit lines have hierarchical structures, where the efficiency of redundancy is increased by replacing a defective memory cell existing in a column or row by a sub word line unit or a sub bit line unit.

Abstract: A semiconductor nonvolatile memory device comprised of bit lines and source lines arranged in a hierarchy of main lines and sub-lines, the main lines and the sub-lines being selectively connected in accordance with the operation of the memory device and memory cells being connected in parallel between the sub-source lines and the sub-bit lines, wherein data is written by introducing electrons from the full channel surface to the charge-storage layer by FN tunneling and is erased by drawing out the electrons in the charge-storing layer from the drain side by FN tunneling. Operation is made possible by a single power source and the area of the cell of the full one transistor memory type is made smaller.

Abstract: A ferroelectric memory which can ensure a sufficient operational margin at the time of a read operation, includes a transmission transistor and a ferroelectric capacitor which are connected in series between a bit line and a plate electrode. Composite data of a pair of reference cells storing reverse data with each other and data of a read cell are compared before reading out data of a memory cell.

Abstract: A ferroelectric non-volatile memory which can ensure a sufficient operational margin, wherein memory cells each constituted by a capacitor using a ferroelectric material for the dielectric film and a select transistor are arranged in a matrix to constitute a so-called folded bit-line structure, when reading out data to either a bit line of an even column or a bit line of an odd column, the other bit line is biased to a constant voltage, and, due to this, the coupling noise from adjoining bit lines is shielded.

Abstract: A ferroelectric memory comprised of a word line; a read bit line; a plate line; a memory array comprised of a matrix arrangement of memory cells with gate electrodes connected to the word line, one of the source-drain electrodes connected to the read bit line, the other of the source-drain electrodes connected to one of the electrodes of a ferroelectric capacitor, and the other of the electrodes of the ferroelectric capacitor connected to the plate line; a first reference cell and a second reference cell corresponding to each of the read cells in a word line selected at the time of reading data, read out in comparison with each other, and storing data different in value from each other; a first sense amplifier for comparing and amplifying a difference in potential between the read bit line and a first reference bit line to which the first reference cell is connected for each read bit line to which a read cell is connected; and a second sense amplifier for comparing and amplifying a difference in potential bet

Abstract: A flash EEPROM, wherein provision is made of an auxiliary bit portion connecting nonvolatile memories in parallel with bit lines of a memory array portion and a spare row decoder for controlling addresses of a redundant memory portion, which records the cumulative number of cycles of rewriting and erasure for each word line in the nonvolatile memories, judges from the stored cumulative number of cycles if the number of cycles of a sector has reached a limit value, and, when reaching it, replaces the word line with a redundant word line so as to prolong the life of the memory even when the cumulative number of cycles of a specific word line has reached a limit value and which stores the data in accordance with different phases when the number of the data "1" or "0" is greater than or less than a predetermined number at the time of writing data and fetches the stored information based on the phase information at the time of reading data so as to reduce the drain disturbances.

Abstract: A semiconductor nonvolatile memory device which is able to be repeatedly rewritten a certain number of times by electrically erasing its memory cells, the semiconductor nonvolatile memory device being comprised of a detecting circuit for detecting if there are any memory cells which had been over-erased (mal-erased) at each rewrite operation, a write circuit for writing, into any cell where over-erasure had been detected, data of a normal or inverted level based on the data which should be written in the over-erased cells, and a recorder for recording if the write circuit wrote the data the same or inverted in level.

Abstract: A flash EEPROM, wherein provision is made of an auxiliary bit portion connecting nonvolatile memories in parallel with bit lines of a memory array portion and a spare row decoder for controlling addresses of a redundant memory portion, which records the cumulative number of cycles of rewriting and erasure for each word line in the nonvolatile memories, judges from the stored cumulative number of cycles if the number of cycles of a sector has reached a limit value, and, when reaching it, replaces the word line with a redundant word line so as to prolong the life of the memory even when the cumulative number of cycles of a specific word line has reached a limit value and which stores the data in accordance with different phases when the number of the data "1" or "0" is greater than or less than a predetermined number at the time of writing data and fetches the stored information based on the phase information at the time of reading data so as to reduce the drain disturbances.