Patents by Inventor Kensuke Fujimoto

Kensuke Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080130437
    Abstract: In an optical disk apparatus using an optical disk having groove tracks and land tracks alternately arranged therein and land pre-pits indicating position information defined in the land tracks, the optical disk is irradiated with a light beam and light reflected from the optical disk is received on divisional light-receiving surfaces to generate a light detection signal for each of the light-receiving surfaces. A pre-pit component signal corresponding to the land pre-pits is generated based on the light detection signals. A binarization-level signal is output. A pre-pit detection signal is generated by comparing the pre-pit component signal with the binarization-level signal. The position information is obtained using the pre-pit detection signal. Pulses of the pre-pit detection signal are counted in units of a period that is based on the position information. The signal level of the binarization-level signal is controlled based on the count values.
    Type: Application
    Filed: May 9, 2007
    Publication date: June 5, 2008
    Applicant: Sony Corporation
    Inventors: Junichi Kanenaga, Kensuke Fujimoto
  • Patent number: 7200094
    Abstract: The present invention provides an apparatus and a method for precisely and adequately evaluating actual quality of reproduced data whenever applying a maximum likelihood decoder for converting signal reproduced from a recording medium into binary signal Based on data arrays of a pair of binary data outputted from a “Viterbi” decoder, SAM values are secured by selecting any of path-metric differential values (00) and (11) being the difference between a pair of values compared when renewing path-metric values PMM (00) and (11) outputted from the “Viterbi” decoder. The minimum SAM value for an ideally-reproduced signal is outputted from a constant generating circuit. If the SAM values are verified as valid, and yet, if the SAM values coincide with the equation “input SAM values”?“data value outputted from the constant generating circuit”, then squared values outputted from a square circuit are averaged by an averaging circuit. Finally, the average value is outputted as the reproduced signal evaluation.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: April 3, 2007
    Assignee: Sony Corporation
    Inventors: Kensuke Fujimoto, Shunji Yoshimura, Atsushi Fukumoto, Yasuhito Tanaka
  • Publication number: 20060215513
    Abstract: The present invention relates to an optical recording method for recording data on an optical disc by using a laser beam. When the optical disc is inserted into an optical recording device (step S1), a test writing area PCA (Power Calibration Area) that can be used for an OPC (Optimum Power Calibration) on the optical disc is searched and an optical pickup is allowed to stand by at that position (step S4). Then, when an input of a recording operation of data is received (step S6), an OPC operation is carried out at the stand-by position (step S7). After an optimum power is obtained, the optical pickup is moved to a data recording area on the optical disc (step S10) to record the data in the data recording area of the optical disc by the optical pickup (step S11).
    Type: Application
    Filed: December 10, 2003
    Publication date: September 28, 2006
    Inventors: Takashi Fujimoto, Masahiro Shigenobu, Kenichiro Aridome, Yasuaki Maeda, Kensuke Fujimoto, Hideki Mawatari
  • Patent number: 6940800
    Abstract: The present invention provides an apparatus and a method for precisely and adequately evaluating actual quality of reproduced data whenever applying a maximum likelihood decoder for converting signal reproduced from a recording medium into binary signal. Based on data arrays of a pair of binary data outputted from a “Viterbi” decoder, SAM values are secured by selecting any of path-metric differential values (00) and (11) being the difference between a pair of values compared when renewing path-metric values PMM (00) and (11) outputted from the “Viterbi” decoder. The minimum SAM value for an ideally-reproduced signal is outputted from a constant generating circuit. If the SAM values are verified as valid, and yet, if the SAM values coincide with the equation “input SAM values”?“data value outputted from the constant generating circuit”, then squared values outputted from a square circuit are averaged by an averaging circuit. Finally, the average value is outputted as the reproduced signal evaluation.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: September 6, 2005
    Assignee: Sony Corporation
    Inventors: Kensuke Fujimoto, Shunji Yoshimura, Atsushi Fukumoto, Yasuhito Tanaka
  • Publication number: 20050190630
    Abstract: The present invention provides an apparatus and a method for precisely and adequately evaluating actual quality of reproduced data whenever applying a maximum likelihood decoder for converting signal reproduced from a recording medium into binary signal Based on data arrays of a pair of binary data outputted from a “Viterbi” decoder, SAM values are secured by selecting any of path-metric differential values (00) and (11) being the difference between a pair of values compared when renewing path-metric values PMM (00) and (11) outputted from the “Viterbi” decoder. The minimum SAM value for an ideally-reproduced signal is outputted from a constant generating circuit. If the SAM values are verified as valid, and yet, if the SAM values coincide with the equation “input SAM values”?“data value outputted from the constant generating circuit”, then squared values outputted from a square circuit are averaged by an averaging circuit. Finally, the average value is outputted as the reproduced signal evaluation.
    Type: Application
    Filed: April 25, 2005
    Publication date: September 1, 2005
    Inventors: Kensuke Fujimoto, Shunji Yoshimura, Atsushi Fukumoto, Yasuhito Tanaka
  • Patent number: 6459669
    Abstract: Light beams are irradiated from a head 2 onto an optical disc 1 including a recording layer and a reproduction (readout) layer to open, at the reproduction layer, detection window smaller than irradiation range of light beams to thereby read out recording information of the recording layer. A resolution detecting section 15 detects resolution on tile basis of signal level of a reproduction signal reproduced from the optical disc 1. A signal level detecting circuit 11 of the resolution detecting section 15 detects signal level of a specific mark length signal corresponding to specific mark length data in the reproduction signal which has been reproduced, and a resolution calculating circuit 12 calculates resolution on the basis of the detected signal level of specific mark length.
    Type: Grant
    Filed: November 23, 1999
    Date of Patent: October 1, 2002
    Assignee: Sony Corporation
    Inventors: Goro Fujita, Kensuke Fujimoto
  • Publication number: 20020114250
    Abstract: The present invention provides an apparatus and a method for precisely and adequately evaluating actual quality of reproduced data whenever applying a maximum likelihood decoder for converting signal reproduced from a recording medium into binary signal. Based on data arrays of a pair of binary data outputted from a “Viterbi” decoder, SAM values are secured by selecting any of path-metric differential values (00) and (11) being the difference between a pair of values compared when renewing path-metric values PMM (00) and (11) outputted from the “Viterbi” decoder. The minimum SAM value for an ideally-reproduced signal is outputted from a constant generating circuit. If the SAM values are verified as valid, and yet, if the SAM values coincide with the equation “input SAM values”≦“data value outputted from the constant generating circuit”, then squared values outputted from a square circuit are averaged by an averaging circuit.
    Type: Application
    Filed: December 14, 2001
    Publication date: August 22, 2002
    Inventors: Kensuke Fujimoto, Shunji Yoshimura, Atsushi Fukumoto, Yasuhito Tanaka
  • Patent number: 6191903
    Abstract: This invention relates to a recording medium, data transmission apparatus, data receiver, and optical disk unit, and particularly applies to a system which transmits video data and other data or records them on an optical disk in a predetermined block unit, and permits each frame to be easily and correctly located by low volumes of identification data. At least contiguous synchronization patterns or/and contiguous synchronization patterns with one synchronization pattern interleaved therebetween are assigned with unique combinations.
    Type: Grant
    Filed: August 11, 1998
    Date of Patent: February 20, 2001
    Assignee: Sony Corporation
    Inventors: Kensuke Fujimoto, Masahiro Shigenobu, Hideki Mawatari
  • Patent number: 6148043
    Abstract: In a branch metric calculating circuit, using a sample value `y` input from an A/D converter and reference levels {-1, -1/2, 1/2, 1}, branch metric calculation is performed by squaring a difference between the sample value `y` and each of the reference levels and subtracting the square of the sample value `y` from the resultant value of squaring the difference. Since actual calculation is carried out for values 2y, y-3/4, -y-3/4 and -2y in this arrangement, square operation circuits can be eliminated, thereby making it possible to simplify a configuration of a Viterbi decoder.
    Type: Grant
    Filed: November 18, 1997
    Date of Patent: November 14, 2000
    Assignee: Sony Corporation
    Inventor: Kensuke Fujimoto
  • Patent number: 6130865
    Abstract: An apparatus and method are provided for moving an optical head to a desired track on a disk shaped recording medium having a pair of spiral tracks. A common address is recorded on the pair of spiral tracks. The addresses of the tracks before and after the access process are compared. Based on this comparison, a judgment is made as to whether the optical head has landed on a spiral track having a common address or a track having another address after the access process.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: October 10, 2000
    Assignee: Sony Corporation
    Inventors: Koji Inoue, Kensuke Fujimoto, Masahiro Shigenobu
  • Patent number: 6130866
    Abstract: A storage medium reproduction apparatus for reproducing data from a storage medium for storing data which are divided into frames of a predetermined length, each of the frames comprising a synchronizing pattern. The apparatus comprises a synchronizing pattern detection circuit for detecting synchronizing patterns and a frame determination circuit for determining a currently reproduced frame on the basis of regularity of the synchronizing patterns detected by the synchronizing pattern detection circuit.
    Type: Grant
    Filed: July 2, 1997
    Date of Patent: October 10, 2000
    Assignee: Sony Corporation
    Inventors: Masahiro Shigenobu, Kensuke Fujimoto, Hirofumi Todo
  • Patent number: 6128256
    Abstract: An apparatus and method are provided for locating a desired track on a disk shaped recording medium. The disk has a first pre-group and a second pre-group. At least one of the pre-groups has encoded address information shared by at least one track on the inner side of the pre-group, and shared by at least one track on an outer side of the pre-group. A desired track is located based on changes in address information detected during or after a track jump.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: October 3, 2000
    Assignee: Sony Corporation
    Inventors: Koji Inoue, Kensuke Fujimoto, Masahiro Shigenobu
  • Patent number: 5987082
    Abstract: To reduce a data-error rate caused by interpolation errors. An adder computes the sum of a sampled value Si+1 of a playback signal and a value 8.times.Si+1 produced by a bit shifter to output the sum 9.times.Si+1 to an adder. The adder adds the sum (9.times.Si+1) supplied thereto by the adder to a sum (9.times.Si) supplied thereto after being delayed by a delay element and outputs the result of the addition (9.times.Si+9.times.Si+1) to an adder. An adder computes the sum of a sampled value Si-1 supplied thereto after being delayed by delay elements and a sampled value Si+2 supplied thereto by an A/D converter and outputs sum (Si-1+Si+2) to the adder. The adder which is used as a subtractor computes the difference between the sum (9.times.Si+9.times.Si+1) supplied thereto by the adder and the sum (Si-1+Si+2) supplied thereto by the adder and outputs the difference (Si-1-9.times.Si-9.times.Si+1+Si+2) to a bit shifter. The bit shifter shifts the difference (Si-1-9.times.Si-9.times.
    Type: Grant
    Filed: July 10, 1997
    Date of Patent: November 16, 1999
    Assignee: Sony Corporation
    Inventor: Kensuke Fujimoto
  • Patent number: 5959947
    Abstract: A simple device and method for accessing a desired track of an optical disk device or the like, wherein address information is encoded on at least one of two pre-groups. One or more tracks adjacent to the pre-groups have the same address. Tracks are located and identified based on changes in address information detected during or after a track jump.
    Type: Grant
    Filed: October 20, 1997
    Date of Patent: September 28, 1999
    Assignee: Sony Corporation
    Inventors: Koji Inoue, Kensuke Fujimoto, Masahiro Shigenobu
  • Patent number: 5917792
    Abstract: An ECC encoder adds sync patterns to a preamble part and a data part in respectively different sequences. A modulator modulates data to which sync patterns have been added by the ECC encoder, and the result is recorded on an optical disk. The playback RF signal output by the optical disk is demodulated by a demodulator, and the sync patterns inserted in the signal are detected. From the combinations of detected sync patterns, the demodulator 12 identifies whether a currently reproduced frame is the preamble part or the data part, and from the identification result, playback data is sequentially stored in a predetermined area of a SRAM. It is thus performed to identify a preamble part from a reproduced RF signal, and accurately extract one block of data.
    Type: Grant
    Filed: July 1, 1997
    Date of Patent: June 29, 1999
    Assignee: Sony Corporation
    Inventors: Masahiro Shigenobu, Kensuke Fujimoto
  • Patent number: 5848047
    Abstract: An A/D converter supplies an interpolation circuit with sampled values which are obtained by sampling a playback signal coming from a read-out device in synchronization with a system clock signal. In the interpolation circuit, the value of the playback signal at the time the phase of a PLL clock phase signal P supplied by a PLL clockphase signal generator becomes zero is computed from the sampled values by using a linear interpolation technique. The interpolation value is then supplied to a binary conversion circuit and fed back to a phase error detecting circuit. The binary conversion circuit converts the interpolation value of the playback signal into a binary value which is then supplied to a circuit at the following stage. The phase error detecting circuit detects a zero cross of the interpolation value of the playback signal. The zero cross timing is then used for computing a phase error signal which is then output to the PLL clock phase signal generator by way of a loop filter.
    Type: Grant
    Filed: July 3, 1997
    Date of Patent: December 8, 1998
    Assignee: Sony Corporation
    Inventor: Kensuke Fujimoto
  • Patent number: 5841323
    Abstract: An A/D converter performs sampling of a reproduced signal from a reading device in synchronism with a clock signal from a PLL circuit and outputs the sampled value to a binary circuit and a phase comparator. The phase comparator detects a change from a positive sampled value to a negative one or from the negative sampled value to a positive one (zero-cross) and outputs a phase error signal corresponding to the zero-cross to a frequency comparator. The frequency comparator outputs a frequency error sensed in reference to a variation of the phase error signal to a switch through a low pass filter. The switch outputs the frequency error to an adder only when the PLL is not in a lock state. The adder outputs a sum of the frequency error and the phase error to a VCO through a loop filter. The VCO generates the clock signal with a frequency corresponding to the sum and supplies it to the A/D converter.
    Type: Grant
    Filed: September 26, 1997
    Date of Patent: November 24, 1998
    Assignee: Sony Corporation
    Inventor: Kensuke Fujimoto