Abstract: A nonvolatile semiconductor memory device comprising: a memory cell array in which two bit lines are provided to each one bit of input data, and memory cells each including an anti-fuse element are arranged at an intersection point between one of the two bit lines and an even address word line, and an intersection point between the other one of the two bit lines and an odd address word line, respectively; a plurality of booster circuits which are arranged in a plurality of memory banks, respectively, and each of which generates a write voltage and a read voltage to be supplied to a corresponding one of the anti-fuse elements of the respective memory banks, each of the memory banks obtained by dividing the memory cell array; a booster circuit controller to issue an instruction to generate the write voltage and the read voltage to the plurality of booster circuits; a word line selector to activate a different word line at the time of writing from one to be activated at the time of reading, with respect to the s

Abstract: A nonvolatile semiconductor memory device comprises an array of memory cells each including an antifuse to store information based on a variation in resistance in accordance with destruction of the insulator in the antifuse. The antifuse includes a semiconductor substrate, a first conduction layer formed in the surface of the semiconductor substrate, a first electrode provided on the first conduction layer to be given a first voltage, a second conduction layer provided on the semiconductor substrate with the insulator interposed therebetween, and a second electrode provided on the second conduction layer to be given a second voltage different from the first voltage. The first electrode or the second electrode is formed of a metal silicide.

Abstract: A nonvolatile semiconductor memory device comprising: a memory cell array in which two bit lines are provided to each one bit of input data, and memory cells each including an anti-fuse element are arranged at an intersection point between one of the two bit lines and an even address word line, and an intersection point between the other one of the two bit lines and an odd address word line, respectively; a plurality of booster circuits which are arranged in a plurality of memory banks, respectively, and each of which generates a write voltage and a read voltage to be supplied to a corresponding one of the anti-fuse elements of the respective memory banks, each of the memory banks obtained by dividing the memory cell array; a booster circuit controller to issue an instruction to generate the write voltage and the read voltage to the plurality of booster circuits; a word line selector to activate a different word line at the time of writing from one to be activated at the time of reading, with respect to the s

Abstract: A memory cell includes: an irreversible storage element that writes data by breaking down an insulating film, with a write voltage being applied to its one end; and first and second transistors with one end being connected to the other end of the irreversible storage element. A non-volatile semiconductor storage device includes: the memory cell; write word lines and read word lines that are connected to the first transistor and the second transistor, respectively; write bit lines and read bit lines that are connected to the first transistor and the other end of the second transistor, respectively; a row decoder selectively driving the write word lines and the read word lines; and a write-disturb prevention circuit charging the read bit lines to a certain voltage in writing data.

Abstract: A write voltage source is capable of applying a write voltage, which is a high voltage. An antifuse is connected at one end to the write voltage source and has a resistance irreversibly variable based on the write voltage. A sense node is connectable to the other end of the antifuse. A sense amp compares the potential on the sense node with a reference potential. The sense node is used to accumulate charge thereon. To control the potential difference placed between both ends of the antifuse, a third transistor is provided having one end connected to the sense node. The third transistor is provided with a precharge voltage source on the other end, and a precharge controller operative to on/off control the gate.

Abstract: A nonvolatile semiconductor memory device comprises an array of memory cells each including an antifuse to store information based on a variation in resistance in accordance with destruction of the insulator in the antifuse. The antifuse includes a semiconductor substrate, a first conduction layer formed in the surface of the semiconductor substrate, a first electrode provided on the first conduction layer to be given a first voltage, a second conduction layer provided on the semiconductor substrate with the insulator interposed therebetween, and a second electrode provided on the second conduction layer to be given a second voltage different from the first voltage. The first electrode or the second electrode is formed of a metal silicide.

Abstract: A memory cell includes: an irreversible storage element that writes data by breaking down an insulating film, with a write voltage being applied to its one end; and first and second transistors with one end being connected to the other end of the irreversible storage element. A non-volatile semiconductor storage device includes: the memory cell; write word lines and read word lines that are connected to the first transistor and the second transistor, respectively; write bit lines and read bit lines that are connected to the first transistor and the other end of the second transistor, respectively; a row decoder selectively driving the write word lines and the read word lines; and a write-disturb prevention circuit charging the read bit lines to a certain voltage in writing data.

Abstract: A write voltage source is capable of applying a write voltage, which is a high voltage. An antifuse is connected at one end to the write voltage source and has a resistance irreversibly variable based on the write voltage. A sense node is connectable to the other end of the antifuse. A sense amp compares the potential on the sense node with a reference potential. The sense node is used to accumulate charge thereon. To control the potential difference placed between both ends of the antifuse, a third transistor is provided having one end connected to the sense node. The third transistor is provided with a precharge voltage source on the other end, and a precharge controller operative to on/off control the gate.