Patents by Inventor Kensuke Nagayama
Kensuke Nagayama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11952460Abstract: A polycarbonate resin having a high refractive index, a low Abbe number and a high moisture and heat resistance is provided. In an embodiment, a polycarbonate resin including a structural unit represented by general formula (1) below is provided.Type: GrantFiled: July 29, 2022Date of Patent: April 9, 2024Assignee: MITSUBISHI GAS CHEMICAL COMPANY, INC.Inventors: Munenori Shiratake, Kentaro Ishihara, Koji Hirose, Shinya Ikeda, Noriyuki Kato, Mitsuteru Kondo, Shoko Suzuki, Kensuke Oshima, Shuya Nagayama
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Patent number: 10716218Abstract: A display device is provided with a laminated wiring including a low-resistance conductive film, a low-reflection film mainly containing Al and functioning as a reflection preventing film, and a cap film which are sequentially laminated on a transparent substrate, and an insulting film formed so as to cover the laminated wiring.Type: GrantFiled: March 8, 2013Date of Patent: July 14, 2020Assignee: Mitsubishi Electric CorporationInventors: Masami Hayashi, Kenichi Miyamoto, Nobuaki Ishiga, Kensuke Nagayama, Naoki Tsumura
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Patent number: 10665616Abstract: A TFT substrate includes: a first semiconductor layer made of a-Si, disposed on a gate insulation layer, facing to a first gate electrode; a first and a second contact layers made of oxide having semiconductor characteristics and each partially disposed in contact with the first semiconductor layer; a first and a second electrodes connected with the first and the second contact layers, respectively; a second semiconductor layer having the same composition as the first contact layer, disposed on the gate insulation layer, facing to a second gate electrode; a third and a fourth electrodes having the same composition as the first electrode and each partially disposed in contact with the second semiconductor layer; and a pixel electrode made of oxide having conductive characteristics and the same composition as the first contact layer, disposed on an insulation layer in a first region, connected with the second electrode.Type: GrantFiled: June 27, 2018Date of Patent: May 26, 2020Assignee: Mitsubishi Electric CorporationInventors: Kazunori Inoue, Koji Oda, Kensuke Nagayama
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Patent number: 10483286Abstract: An array substrate according to the present invention is a TFT substrate including a pixel TFT and a drive TFT on a substrate, where the pixel TFT includes a first source electrode, a first drain electrode, and an amorphous silicon layer, and the drive TFT includes a third oxide semiconductor layer provided on a gate insulating film while overlapping a second gate electrode in plan view, and a second source electrode and a second drain electrode overlapping the third oxide semiconductor layer in plan view, with a third separation portion separating the second source electrode and the second drain electrode from each other.Type: GrantFiled: February 27, 2018Date of Patent: November 19, 2019Assignee: Mitsubishi Electric CorporationInventors: Koji Oda, Kazunori Inoue, Kensuke Nagayama
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Publication number: 20190013333Abstract: A TFT substrate includes: a first semiconductor layer made of a-Si, disposed on a gate insulation layer, facing to a first gate electrode; a first and a second contact layers made of oxide having semiconductor characteristics and each partially disposed in contact with the first semiconductor layer; a first and a second electrodes connected with the first and the second contact layers, respectively; a second semiconductor layer having the same composition as the first contact layer, disposed on the gate insulation layer, facing to a second gate electrode; a third and a fourth electrodes having the same composition as the first electrode and each partially disposed in contact with the second semiconductor layer; and a pixel electrode made of oxide having conductive characteristics and the same composition as the first contact layer, disposed on an insulation layer in a first region, connected with the second electrode.Type: ApplicationFiled: June 27, 2018Publication date: January 10, 2019Applicant: Mitsubishi Electric CorporationInventors: Kazunori INOUE, Koji ODA, Kensuke NAGAYAMA
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Patent number: 10128270Abstract: The present disclosure relates to a method for manufacturing an active matrix substrate. A first laminated film in which a semiconductor film, a first transparent conductive film, and a first metal film are laminated is formed on a substrate. A photoresist pattern having a first part covering a formation area of a channel part of a thin film transistor, a second part covering a formation area of a pixel electrode, and a third part covering formation areas of a source electrode, a drain electrode, and a source line, is formed on the first laminated film. The first metal film, the first transparent conductive film, and the semiconductor film are patterned using the photoresist pattern; the first part is removed and the first metal film and the first transparent conductive film are patterned; and the second part is removed and the first metal film is patterned.Type: GrantFiled: November 17, 2016Date of Patent: November 13, 2018Assignee: Mitsubishi Electric CorporationInventors: Nobuaki Ishiga, Kazunori Inoue, Naoki Tsumura, Kensuke Nagayama, Yasuyoshi Ito
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Publication number: 20180277661Abstract: A first semiconductor layer is opposed to a first gate electrode with intermediation of a gate insulation film, and is formed of amorphous silicon. First and second contact layers each have a portion arranged on the first semiconductor layer, and are formed of an oxide semiconductor. A first electrode is connected to the first contact layer. A second electrode is connected to the second contact layer.Type: ApplicationFiled: March 8, 2018Publication date: September 27, 2018Applicant: Mitsubishi Electric CorporationInventors: Kensuke NAGAYAMA, Kazunori INOUE, Koji ODA
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Publication number: 20180261631Abstract: An array substrate according to the present invention is a TFT substrate including a pixel TFT and a drive TFT on a substrate, where the pixel TFT includes a first source electrode, a first drain electrode, and an amorphous silicon layer, and the drive TFT includes a third oxide semiconductor layer provided on a gate insulating film while overlapping a second gate electrode in plan view, and a second source electrode and a second drain electrode overlapping the third oxide semiconductor layer in plan view, with a third separation portion separating the second source electrode and the second drain electrode from each other.Type: ApplicationFiled: February 27, 2018Publication date: September 13, 2018Applicant: Mitsubishi Electric CorporationInventors: Koji ODA, Kazunori INOUE, Kensuke NAGAYAMA
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Patent number: 9929186Abstract: A thin film transistor substrate includes: a thin film transistor including: a first insulating film covering a gate electrode; a semiconductor channel layer selectively provided on the first insulating film; a second insulating film provided on the semiconductor channel layer; a first source electrode and a first drain electrode selectively provided on the second insulating film, a second source electrode and a second drain electrode provided on the first source electrode and the first drain electrode, respectively, a third insulating film that covers the second source electrode and the second drain electrode; a third source electrode connected to the semiconductor channel layer via a first contact hole provided through the third insulating film, the second and the first source electrode; a third drain electrode connected to the semiconductor channel layer via a second contact hole provided through the third insulating film, the second drain electrode, and the first drain electrode.Type: GrantFiled: March 15, 2017Date of Patent: March 27, 2018Assignee: Mitsubishi Electric CorporationInventors: Takaharu Konomi, Kazunori Inoue, Naoki Tsumura, Kensuke Nagayama
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Patent number: 9910199Abstract: A display includes: a laminated wiring with a conductive film arranged on a foundation layer, and a transparent film and a translucent film arranged on the conductive film; a wiring terminal part arranged at an edge portion of the laminated wiring and having the same laminated structure as that of the laminated wiring; and an insulating film that covers the laminated wiring and the wiring terminal part.Type: GrantFiled: August 19, 2016Date of Patent: March 6, 2018Assignee: Mitsubishi Electric CorporationInventors: Masami Hayashi, Kenichi Miyamoto, Nobuaki Ishiga, Naoki Tsumura, Kensuke Nagayama
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Publication number: 20170278866Abstract: A thin film transistor substrate includes: a thin film transistor including: a first insulating film covering a gate electrode; a semiconductor channel layer selectively provided on the first insulating film; a second insulating film provided on the semiconductor channel layer; a first source electrode and a first drain electrode selectively provided on the second insulating film, a second source electrode and a second drain electrode provided on the first source electrode and the first drain electrode, respectively, a third insulating film that covers the second source electrode and the second drain electrode; a third source electrode connected to the semiconductor channel layer via a first contact hole provided through the third insulating film, the second and the first source electrode; a third drain electrode connected to the semiconductor channel layer via a second contact hole provided through the third insulating film, the second drain electrode, and the first drain electrode.Type: ApplicationFiled: March 15, 2017Publication date: September 28, 2017Applicant: Mitsubishi Electric CorporationInventors: Takaharu KONOMI, Kazunori INOUE, Naoki TSUMURA, Kensuke NAGAYAMA
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Patent number: 9673232Abstract: An oxide semiconductor film and an oxide conductive film are stacked to form a semiconductor layer. The oxide conductive film is made of a material by which the oxide conductive film is etched at a higher speed than the oxide semiconductor film for example with a PAN chemical containing phosphoric acid, nitric acid, and acetic acid. A source electrode and a drain electrode are electrically connected to the oxide semiconductor film through the oxide conductive film at least at an end portion of the source electrode and an end portion of the drain electrode facing each other. A channel region made of the oxide semiconductor film is formed between the source electrode and the drain electrode. The oxide semiconductor film has a substantially tapered shape in cross section at an end face thereof.Type: GrantFiled: June 8, 2015Date of Patent: June 6, 2017Assignee: Mitsubishi Electric CorporationInventors: Naoki Tsumura, Kensuke Nagayama, Nobuaki Ishiga, Kazunori Inoue
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Publication number: 20170069665Abstract: To reduce the number of photolithography processes in manufacturing an active matrix substrate. Provided is a TFT substrate which has a pixel electrode connected to a drain electrode of a TFT, a source line connected to a source electrode of the TFT, and a gate line connected to a gate electrode of the TFT. A source electrode, a drain electrode, and a source line include a conductive film of the same layer as the pixel electrode. Under the source line and the pixel electrode, there remains a semiconductor layer of the same layer as a semiconductor film which constitutes a channel part of the TFT substrate.Type: ApplicationFiled: November 17, 2016Publication date: March 9, 2017Applicant: Mitsubishi Electric CorporationInventors: Nobuaki ISHIGA, Kazunori INOUE, Naoki TSUMURA, Kensuke NAGAYAMA, Yasuyoshi ITO
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Publication number: 20160356933Abstract: A display includes: a laminated wiring with a conductive film arranged on a foundation layer, and a transparent film and a translucent film arranged on the conductive film; a wiring terminal part arranged at an edge portion of the laminated wiring and having the same laminated structure as that of the laminated wiring; and an insulating film that covers the laminated wiring and the wiring terminal part.Type: ApplicationFiled: August 19, 2016Publication date: December 8, 2016Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Masami HAYASHI, Kenichi MIYAMOTO, Nobuaki ISHIGA, Naoki TSUMURA, Kensuke NAGAYAMA
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Patent number: 9508750Abstract: A gate wiring, a source electrode, a source-electrode connecting wiring, a pixel electrode, a gate-terminal extraction electrode, and a source-terminal extraction electrode are formed in the same layer on a planarization insulating film. The gate wiring is connected to a gate electrode through a gate-electrode-portion contact hole. The source electrode is connected to a semiconductor film through a source-electrode-portion contact hole. The source-electrode connecting wiring is connected to the semiconductor film and a source wiring through the source-electrode-portion contact hole and a source-wiring-portion contact hole, respectively. The pixel electrode is connected to the semiconductor film through a drain (pixel)-electrode-portion contact hole.Type: GrantFiled: November 25, 2014Date of Patent: November 29, 2016Assignee: Mitsubishi Electric CorporationInventors: Kyosuke Hiwatashi, Kazunori Inoue, Kouji Oda, Nobuaki Ishiga, Kensuke Nagayama, Naoki Tsumura
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Patent number: 9461077Abstract: A thin film transistor includes: a semiconductor channel film; a gate insulating film on the semiconductor channel film; a gate electrode formed of a laminated film including a first conductive film and a second conductive film on the gate insulating film; an interlayer insulating film covering the semiconductor channel film, the gate insulating film, and the gate electrode; a source electrode formed of a laminated film including a third conductive film and a fourth conductive film formed on the interlayer insulating film; and a drain electrode formed of the third conductive film. A gate wiring is formed of the laminated film including the first conductive film and the second conductive film. A source wiring is formed of the laminated film including the third conductive film and the fourth conductive film. A pixel electrode is formed of the first conductive film. A counter electrode is formed of the third conductive film.Type: GrantFiled: August 31, 2015Date of Patent: October 4, 2016Assignee: Mitsubishi Electric CorporationInventors: Kazunori Inoue, Nobuaki Ishiga, Kensuke Nagayama, Naoki Tsumura
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Patent number: 9459380Abstract: A display includes: a laminated wiring with a conductive film arranged on a foundation layer, and a transparent film and a translucent film arranged on the conductive film; a wiring terminal part arranged at an edge portion of the laminated wiring and having the same laminated structure as that of the laminated wiring; and an insulating film that covers the laminated wiring and the wiring terminal part.Type: GrantFiled: December 4, 2015Date of Patent: October 4, 2016Assignee: Mitsubishi Electric CorporationInventors: Masami Hayashi, Kenichi Miyamoto, Nobuaki Ishiga, Naoki Tsumura, Kensuke Nagayama
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Patent number: 9343487Abstract: A TFT substrate includes a TFT including a source electrode having a lower source electrode and an upper source electrode, which are electrically connected to each other, and a drain electrode having a lower drain electrode and an upper drain electrode, which are electrically connected to each other. The lower source electrode and the lower drain electrode are in contact with a lower surface of the semiconductor film, and the upper source electrode and the upper drain electrode are in contact with an upper surface of the semiconductor film.Type: GrantFiled: August 28, 2015Date of Patent: May 17, 2016Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Kensuke Nagayama, Kazunori Inoue, Yasuyoshi Ito, Nobuaki Ishiga, Naoki Tsumura, Shinichi Yano
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Publication number: 20160084992Abstract: A display includes: a laminated wiring with a conductive film arranged on a foundation layer, and a transparent film and a translucent film arranged on the conductive film; a wiring terminal part arranged at an edge portion of the laminated wiring and having the same laminated structure as that of the laminated wiring; and an insulating film that covers the laminated wiring and the wiring terminal part.Type: ApplicationFiled: December 4, 2015Publication date: March 24, 2016Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Masami HAYASHI, Kenichi MIYAMOTO, Nobuaki ISHIGA, Naoki TSUMURA, Kensuke NAGAYAMA
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Patent number: 9250363Abstract: A display includes: a laminated wiring with a conductive film arranged on a foundation layer, and a transparent film and a translucent film arranged on the conductive film; a wiring terminal part arranged at an edge portion of the laminated wiring and having the same laminated structure as that of the laminated wiring; and an insulating film that covers the laminated wiring and the wiring terminal part.Type: GrantFiled: October 4, 2013Date of Patent: February 2, 2016Assignee: Mitsubishi Electric CorporationInventors: Masami Hayashi, Kenichi Miyamoto, Nobuaki Ishiga, Naoki Tsumura, Kensuke Nagayama