Abstract: An apparatus and method for replacing a CPU cooling system, for example, a fan, while a computer continues to operate has a mechanism for maintenance personnel to signal that cooling fan replacement is about to begin. In response to the signal, a control mechanism causes the CPU to shift into an operating mode in which heat generation is reduced. In some cases, a clock frequency of the affected CPU and/or a duty cycle at which the CPU operates is reduced. After the fan has been replaced the control mechanism returns the CPU to a normal operational mode, for example, by increasing the clock frequency or duty cycle to a normal level. During the fan replacement procedure, the CPU and its software continues to run at lower than normal performance.

Abstract: Compute nodes in a high performance computer system are interconnected by an inter-node communication network. Each compute node has a network interface coupled directly to a CPU by a dedicated full-duplex packetized interconnect. Data may be exchanged between compute nodes using eager or rendezvous protocols. The network interfaces may include facilities to manage data transfer between computer nodes.

Abstract: An apparatus and method for replacing a CPU cooling system, for example, a fan, while a computer continues to operate has a mechanism for maintenance personnel to signal that cooling fan replacement is about to begin. In response to the signal, a control mechanism causes the CPU to shift into an operating mode in which heat generation is reduced. In some cases, a clock frequency of the affected CPU and/or a duty cycle at which the CPU operates is reduced. After the fan has been replaced the control mechanism returns the CPU to a normal operational mode, for example, by increasing the clock frequency or duty cycle to a normal level. During the fan replacement procedure, the CPU and its software continues to run at lower than normal performance.

Abstract: A method of minimizing throughput delay in constant-bit-rate services carried over packet-based networks subject to variable delays, comprises, in one embodiment, the steps of receiving incoming packets in a buffer, reading out bits from the buffer at a clock frequency fi, continually monitoring the buffer fill level Li, determining the maximum fill level Lmaxj over a plurality of successive samples, determining the minimum fill level Lmink over a plurality of successive samples, adjusting the clock frequency fi to cause the maximum fill level Lmaxj to tend toward a target value TargetLmax, and adaptively changing said target value TargetLmax so that the minimum fill level Lmink tends toward a predetermined set-point. The rate of change of the target value TargetLmax is significantly slower than the rate of adjustment of clock frequency. The invention can be applied to other types of clock recovery.