Abstract: In some examples, a protocol accelerator extracts a queue identifier from an incoming packet, for identifying a first buffer queue in which the packet is to be stored for transport layer processing. A packet having an error or condition is identified, such that the accelerator cannot perform the processing on that packet. A processor is interrupted. The identified packet is stored in a second buffer queue. The processor performs transport layer processing in response to the interrupt, while the accelerator continues transport layer processing of packets in the first buffer queue. In some examples, a TCP congestion window size is adjusted. A programmable congestion window increment value is provided. The window size is set to an initial value at the beginning of a TCP data transmission. The window size is increased by the increment value when an acknowledgement is received.

Abstract: An apparatus and method are provided for extracting connection information from a traffic header in a communications network. The apparatus includes a first storage element containing a first look-up table for determining a first data packet header offset and data size for extracting a communications protocol type from the header and a second storage element containing a second look-up table for determining from the communications protocol type a second data packet header offset and second data size for extracting a connection address from the header. The storage elements may be in the form of content-addressable memories. Exception handling and hardware initialization can be controlled by a system processor.

Abstract: A hardware accelerated streaming arrangement, especially for RTP real time protocol streaming, employs a directing file determining the pointers, header lengths and offsets of a block of one or more data packets to be sent out through a network accelerated streaming system. The directing file is established by a control processor, for example working in the background, and is stored to provide information making it possible to determine certain information including header sizes and pointers to RTP payload and other data, without the need during egress of the data for analysis related to the type of media or protocol concerned.

Abstract: A hardware accelerated streaming arrangement, especially for RTP real time protocol streaming, directs data packets for one or more streams between sources and destinations, using addressing and handling criteria that are determined in part from control packets and are used to alter or supplement headers associated with the stream content packets. A programmed control processor responds to control packets in RTCP or RTSP format, whereby the handling or direction of RTP packets can be changed. The control processor stores data for the new addressing and handling criteria in a memory accessible to a hardware accelerator, arranged to store the criteria for multiple ongoing streams at the same time. When a content packet is received, its addressing and handling criteria are found in the memory and applied, by action of the network accelerator, without the need for computation by the control processor.

Abstract: The present invention provides a reduction checksum generator for calculating a checksum value for a block of data. In one embodiment, the reduction checksum generator includes a reduction unit having a plurality of reduction stages and configured to pipeline a plurality of segments of the block of data through the plurality of reductions stages to reduce the plurality of segments to at least two segments. The reduction checksum generator also includes a checksum unit configured to generate a one's complement sum of the at least two segments and invert the one's complement sum to produce the checksum value. In addition, a method of calculating checksum value using reduction for a block of data and a parallel reduction checksum generator are also disclosed.

Abstract: A checksum calculator employs a tree structure of reduction stages to process words of a checksum data array. The number of words in the checksum data array is compared to the number of words each of the reduction stages might process. If the number of words in the checksum data array is greater than the number of words that the highest level reduction stage might process, then a portion of the checksum data array is processed, remaining words of the checksum data array are appended to the processed portion, and the process is repeated. If the number of words in the checksum data array is less than or equal to the number of words that the highest level reduction stage might process, then the checksum data array is processed by the lowest level reduction stage that can process the entire checksum data array.

Abstract: The invention provides techniques for reducing the power consumption of pipelined processors. In an illustrative embodiment, the invention evaluates the predicates of predicated instructions in a decode stage of a pipelined processor, and annuls instructions with false predicates before those instructions can be processed by subsequent stages, e.g, by execute and writeback stages. The predicate dependencies can be handled using, e.g., a virtual single-cycle execution technique which locks a predicate register while the register is in use by a given instruction, and then stalls subsequent instructions that depend on a value stored in the register until the register is unlocked. As another example, the predicate dependencies can be handled using a compiler-controlled dynamic dispatch (CCDD) technique, which identifies dependencies associated with a set of instructions during compilation of the instructions in a compiler.

Abstract: The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A cooperative interconnection technique in accordance with the invention utilizes an inter-cluster move instruction specifying a source cluster and a destination cluster to copy a value from the source cluster to the destination cluster. The value is transmitted over a designated interconnect structure within the processor, and the inter-cluster move instruction is separated into two sub-instructions, one of which is executed by a unit in the source cluster, and another of which is executed by a unit in the destination cluster. These units may be, e.g.

Abstract: The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A duplicator interconnection technique in accordance with the invention reduces port pressure by providing one or more global move units in the processor. A given global move unit uses an inter-cluster move instruction to copy a value from a portion of the register or predicate file associated with a source cluster to another portion of the register or predicate file associated with a destination cluster.

Abstract: The invention provides techniques for improving the performance of pipelined processors by eliminating unnecessary stalling of instructions. In an illustrative embodiment, a compiler is used to identify pipeline dependencies in a given set of instructions. The compiler then groups the set of instructions into a code block having a field which indicates the types of pipeline dependencies, if any, in the set of instructions. The field may indicate the types of pipeline dependencies by specifying which of a predetermined set of hazards arise in the plurality of instructions when executed on a given pipelined processor. For example, the field may indicate whether the code block includes any Read After Write (RAW) hazards, Write After Write (WAW) hazards or Write After Read (WAR) hazards. The code block may include one or more dynamic scheduling instructions, with each of the dynamic scheduling instructions including a set of instructions for execution in a multi-issue processor.

Abstract: A processor is configured to include at least two architecturally-distinct storage spaces, such as, for example, a stack for storing control operands associated with one or more instructions, and a register file for storing computational operands associated with one or more instructions. The processor further includes a datapath which is at least partially shared by the stack and register file, a multiplexer operative to select an output of either the stack or the register file for application to an input of the shared datapath, and a demultiplexer operative to select an output of the shared datapath for application to an input of either the stack or the register file.

Abstract: The invention provides techniques for reducing the port pressure of a clustered processor. In an illustrative embodiment, the processor includes multiple clusters of execution units, with each of the clusters having a portion of a register file and a portion of a predicate file associated therewith, such that a given cluster is permitted to write to and read from its associated portions of the register and predicate files. A replication technique in accordance with the invention reduces port pressure by replicating, e.g., a register lock file and a predicate lock file of the processor for each of the clusters. The replicated files vary depending upon whether the technique is implemented with a write-only interconnection or a read-only interconnection.