Abstract: A cooling apparatus including a heat sink to which a heat generating body is joined, a main flow generation device configured to generate a main flow for cooling the heat sink, and an induced flow generation device configured to electrically generate an induced flow. The induced flow generation device is provided to a support member facing the heat sink.

Abstract: Provide is a distillation tower management system, a distillation tower state analysis method, and a distillation tower management method that are capable of predicting abnormality in distillation towers before the abnormality becomes apparent and capable of taking preventive actions. The distillation tower management system includes a measurement unit 10 that is at least one selected from the group consisting of a pressure measurement unit 11, a temperature measurement unit 12 and a chlorine measurement unit 13, an operation data unit 20 for producing operation data containing measurement data measured with the measurement unit 10, an analysis unit 30 for analyzing the state of a distillation tower 103 from the operation data and producing analysis data regarding the state of the distillation tower 103, and a control unit 40 for producing, based on the analysis data, control data regarding a differential pressure-eliminating agent that is added to the distillation tower 103.

Abstract: A method for eliminating pressure loss (pressure difference) caused by salt derived from impurities in raw materials in a distillation facility during operation without negative effect on the quality of products and production efficiency is provided. The method for eliminating occurrence of pressure difference caused by precipitation of salt in a distillation facility includes using a specific quaternary ammonium compound.

Abstract: The semiconductor device includes at least three semiconductor elements disposed directly or indirectly on a planar member and constituting an upper arm and a lower arm which perform ON and OFF action at mutually differential times; an upper-surface voltage applied region of each semiconductor element is configured to be narrower than an area of the aforementioned whole semiconductor element in planar view; and each semiconductor element is disposed so that the shortest distance between the semiconductor elements constituting the upper arm is formed so as to be longer than the shortest distance between the semiconductor element constituting the upper arm and the semiconductor element constituting the lower arm.

Abstract: A cooling apparatus including a heat sink to which a heat generating body is joined, a main flow generation device configured to generate a main flow for cooling the heat sink, and an induced flow generation device configured to electrically generate an induced flow. The induced flow generation device is provided to a support member facing the heat sink.

Abstract: The semiconductor device includes at least three semiconductor elements disposed directly or indirectly on a planar member and constituting an upper arm and a lower arm which perform ON and OFF action at mutually differential times; an upper-surface voltage applied region of each semiconductor element is configured to be narrower than an area of the aforementioned whole semiconductor element in planar view; and each semiconductor element is disposed so that the shortest distance between the semiconductor elements constituting the upper arm is formed so as to be longer than the shortest distance between the semiconductor element constituting the upper arm and the semiconductor element constituting the lower arm.

Abstract: The semiconductor device includes: a substrate, an n-type drift region formed on a main surface of the substrate; a p-type well region, an n-type drain region and an n-type source region each formed in the drift region to extend from a second main surface of the drift region opposite to the first main surface of the drift region in contact with the substrate in a direction perpendicular to the second main surface; a gate groove extending from the second main surface in the perpendicular direction and penetrating the source region and the well region in a direction parallel to the first main surface of the substrate; and a gate electrode formed on a surface of the gate groove with a gate insulating film interposed therebetween, wherein the drift region has a higher impurity concentration than the substrate, and the well region extends to the inside of the substrate.

Abstract: A semiconductor device (100) comprises: a semiconductor substrate (1); a drift region (2) of a first conductivity type having a trench in part of an upper portion thereof and arranged on a first main surface of the semiconductor substrate (100); an electric field reducing region (4) of a second conductivity type arranged, in a bottom portion of the trench, only around a corner portion and not in a center portion; an anode electrode (9) embedded in the trench; and a cathode electrode (10) arranged on a second main surface of the semiconductor substrate (100) which is opposite to the first main surface.

Abstract: The semiconductor device includes: a substrate, an n-type drift region formed on a main surface of the substrate; a p-type well region, an n-type drain region and an n-type source region each formed in the drift region to extend from a second main surface of the drift region opposite to the first main surface of the drift region in contact with the substrate in a direction perpendicular to the second main surface; a gate groove extending from the second main surface in the perpendicular direction and penetrating the source region and the well region in a direction parallel to the first main surface of the substrate; and a gate electrode formed on a surface of the gate groove with a gate insulating film interposed therebetween, wherein the drift region has a higher impurity concentration than the substrate, and the well region extends to the inside of the substrate.

Abstract: A semiconductor device (100) comprises: a semiconductor substrate (1); a drift region (2) of a first conductivity type having a trench in part of an upper portion thereof and arranged on a first main surface of the semiconductor substrate (100); an electric field reducing region (4) of a second conductivity type arranged, in a bottom portion of the trench, only around a corner portion and not in a center portion; an anode electrode (9) embedded in the trench; and a cathode electrode (10) arranged on a second main surface of the semiconductor substrate (100) which is opposite to the first main surface.