Abstract: A bias circuit supplies a bias voltage VBIAS to a microphone. A variable gain amplifier amplifies a reference voltage VREF. A low-pass filter removes a high-frequency component from the output of the variable gain amplifier. A voltage follower amplifier receives the output voltage of the low-pass filter, and supplies the output voltage to the microphone.

Abstract: Extracting a tubular structure from volume data, determining a target region which should be reached by an endoscope through the tubular structure, extracting, among plurality on a route of the tubular structure, a point that satisfies a given condition as a target point that should be reached by a distal end portion of the endoscope, and identifying and determining a route of the tubular structure from a predetermined start point in the tubular structure to the extracted target point as a route through which the endoscope should be passed.

Abstract: In a computer with a touch panel, displaying a plurality of images on the touch panel using a display parameter preset to each image, and changing, when a touch gesture associated with changing the display parameter is performed on the touch panel for any one of the plurality of displayed images, the display parameter according to the touch gesture for all of the images other than an image somewhere in the display area of which is being pressed when the touch gesture is performed.

Abstract: Providing a parameter calculation unit that calculates parameters representing medical functional information for pixel positions of the medical image, wherein the upper and lower limit values of the parameter medically represent the same functional information and whose value changes cyclically between these values, an interpolation parameter calculation unit that obtains, for a pixel position for which the parameter is not calculated, a parameter by interpolation, the unit calculating a parameter obtained by the interpolation using a cyclic function in which the interpolation direction differs according to the difference between the parameters calculated for two pixel positions, a display color group storage unit that includes a color group in which the same color corresponds to the upper and lower limit values of the parameter and whose color changes with the magnitude of the parameter, and a mapping unit that maps the parameters based on the color group.

Abstract: According to an embodiment, a non-volatile memory device includes a memory cell including a semiconductor layer, a charge storage layer provided on the semiconductor layer, and a first insulating film provided between the semiconductor layer and the charge storage layer. The device also includes a first conductive layer provided on the charge storage layer, a second conductive layer provided between the charge storage layer and the first conductive layer, a second insulating film provided between the charge storage layer and the second conductive layer, and a third insulating film provided between the first conductive layer and the second conductive layer.

Abstract: A nonvolatile semiconductor storage device is provided with a memory-cell region; a peripheral-circuit region disposed adjacent to the memory-cell region a first memory-cell unit disposed in a first layer located in the memory-cell region; a second memory-cell unit disposed in a k-th layer of the memory-cell region where k is an integer equal to or greater than 2, the second memory-cell unit having an element region extending in a first direction and having a first width in a second direction crossing the first direction; and a peripheral-circuit element disposed in the first layer located in the peripheral-circuit region. Two or more dummy element each having a second width 2n+1 times greater than the first width in the second direction are disposed in the k-th layer located in the peripheral-circuit region where n is an integer equal to or greater than 0.

Abstract: Provided is a process for producing a welded joint which includes a weld metal having high strength and high toughness, and containing fewer blowholes. The process for producing a welded joint according to the present embodiment includes the steps of: preparing a base material containing, by mass %, not less than 10.5% of Cr; and subjecting the base material to GMA welding using a shielding gas containing 1 to 2 volume % or 35 to 50 volume % of CO2 gas, and the balance being inert gas, thereby forming a weld metal includes, by mass %, C: not more than 0.080%, Si: 0.20 to 1.00%, Mn: not more than 8.00%, P: not more than 0.040%, S: not more than 0.0100%, Cu: not more than 2.0%, Cr: 20.0 to 30.0%, Ni: 7.00 to 12.00%, N: 0.100 to 0.350%, O: 0.02 to 0.11%, sol. Al: not more, than 0.040%, at least one of Mo: 1.00 to 4.00% and W: 1.00 to 4.00%, and the balance being Fe and impurities.

Abstract: According to an embodiment, a nonvolatile memory device includes a memory cell string, a control gate, first and second insulating films. The memory cell string includes a semiconductor layer and a plurality of memory cells disposed on the semiconductor layer. The control gate is provided on each of the memory cells. The first insulating film covers each side surface of the memory cells, and a side surface of the control gate. The second insulating film covering an upper portion of the control gate is provided on each of two adjacent memory cells. A first air gap is disposed between the two adjacent memory cells and surround by the first insulating film and the second insulating film, and the semiconductor layer is exposed by the first gap, or thickness of an insulating film between the first gap and the semiconductor layer is thinner than the first insulating film.

Abstract: According to an embodiment, a non-volatile memory device includes a memory cell including a semiconductor layer, a charge storage layer provided on the semiconductor layer, and a first insulating film provided between the semiconductor layer and the charge storage layer. The device also includes a first conductive layer provided on the charge storage layer, a second conductive layer provided between the charge storage layer and the first conductive layer, a second insulating film provided between the charge storage layer and the second conductive layer, and a third insulating film provided between the first conductive layer and the second conductive layer.

Abstract: Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.

Abstract: A welded joint of duplex stainless steel, which can suppress precipitation of ? phase under high heat input welding, is excellent in SCC resistance under high-temperature chloride environments. A weld metal of the welded joint contains, in mass percent, C: at most 0.030%, Si: 0.20 to 1.00%, Mn: at most 8.00%, P: at most 0.040%, S: at most 0.0100%, Cu: at most 2.00%, Ni: 7.00 to 12.00%, Cr: 20.0 to 30.0%, Mo: 1 to 4%, N: 0.100 to 0.350%, sol. Al: at most 0.040%, and O: at most 0.035%, the balance being Fe and impurities. The weld metal satisfies Expressions (1) and (3): 2.2Cr+7Mo+3Cu>66??(1) Cr+11Mo+10Ni?12(Cu+30N)<100??(3) where a content (mass percent) of each element in one of the base metal and weld metal is used for each element in Expressions (1) and (3).

Abstract: A duplex stainless steel, which can suppress precipitation of a ? phase under high heat input welding, is excellent in SCC resistance under high-temperature chloride environments and has a high strength. The duplex stainless steel includes a chemical composition containing, in mass percent, C: at most 0.030%, Si: 0.20 to 1.00%, Mn: at most 8.00%, P: at most 0.040%, S: at most 0.0100%, Cu: more than 2.00% and at most 4.00%, Ni: 4.00 to 8.00%, Cr: 20.0 to 28.0%, Mo: 0.50 to 2.00%, N: 0.100 to 0.350%, and sol. Al: at most 0.040%, the balance being Fe and impurities, and satisfying Expression (1) and Expression (2); a structure having a ferrite rate of at least 50%; and a yield strength of at least 550 MPa or more: 2.

Abstract: Provided is a duplex stainless steel having a high strength and a high toughness. A stainless steel according to the present invention includes: a chemical composition containing, in mass percent, C: at most 0.030%, Si: 0.20 to 1.00%, Mn: at most 8.00%, P: at most 0.040%, S: at most 0.0100%, Cu: more than 2.00% and at most 4.00%, Ni: 4.00 to 8.00%, Cr: 20.0 to 30.0%, Mo: at least 0.50% and less than 2.00%, N: 0.100 to 0.350%, and sol. Al: at most 0.040%, the balance being Fe and impurities; and a structure, wherein a rate of ferrite in the structure is 30 to 70%, and a hardness of the ferrite in the structure is at least 300 Hv10gf.

Abstract: A semiconductor device has a semiconductor substrate, a pair of select gate transistors provided on a first region of the semiconductor substrate, a plurality of memory cell transistors provided on a second region provided between the pair of select gate transistors on the semiconductor substrate, a gate electrode of each of the memory cell transistors, the gate electrode provided on the second region via a first insulating film, and including a charge storage layer, an intermediate insulating film, and a control gate electrode film stacked therein, a groove exposed a sidewall of the semiconductor substrate on the first region; and a gate electrode of each of the select gate transistors, the gate electrode including the control gate electrode film formed on the sidewall via a second insulating film.

Abstract: A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a well resistor comprising a terminal region and a main body; and a plurality of contacts formed above the terminal region, the simulation method comprising: modeling a parasitic resistance Rt0 of the terminal region between the plurality of contacts and the main body by the following formula, where ?0, L?0, W?0 are fitting parameters; L? is a length of the terminal region in the longitudinal direction of the well resistor; and W? is a width of the terminal region in the width direction of the well resistor.

Abstract: A exemplary aspect of the present invention is a simulation method for a semiconductor circuit that includes: a semiconductor resistor; a plurality of contacts arranged at regular intervals in a longitudinal direction and in a width direction of the semiconductor resistor on a terminal region of the semiconductor resistor; and a wiring line formed on the plurality of contacts, the simulation method including: defining a ratio of a parasitic-resistance by the semiconductor resistor between two of the contacts neighboring in the longitudinal direction to a resistance of one of the plurality of contacts as a constant k; and modeling a parasitic-resistance net by using the constant k, the parasitic-resistance net including the terminal region of the semiconductor resistor and the plurality of contacts.

Abstract: Nonvolatile semiconductor memory device includes first memory cell array layer, first insulating layer formed thereabove, and second memory cell array layer formed thereabove. First memory cell array layer includes first NAND cell units each including plural first memory cells. The first memory cell includes first semiconductor layer, first gate insulating film formed thereabove, and first charge accumulation layer formed thereabove. The second memory cell array layer includes second NAND cell units each including plural second memory cells. The second memory cell includes second charge accumulation layer, second gate insulating film formed thereabove, and second semiconductor layer formed thereabove. Control gates are formed, via an inter-gate insulating film, on first-direction both sides of the first and second charge accumulation layers positioned the latter above the former via the first insulating layer. The control gates extend in a second direction perpendicular to the first direction.

Abstract: A software product including codes for the method of determining parasitic resistance and capacitance from a layout of an LSI is executed by a computer. The method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection; and by producing a library configured to store parameters indicating the parasitic resistance and the parasitic capacitance in relation to the target interconnection to each of the plurality of patterns. The producing is achieved by calculating the parameters to a plurality of conditions corresponding to deviation in manufacture of the wiring structure for each of the plurality of patterns.

Abstract: A method of designing a semiconductor integrated circuit includes: performing a circuit simulation of a cell with changing a parameter that specifies a layout pattern around the cell; and generating a delay function expressing a delay value of the cell as a function of the parameter, based on a result of the circuit simulation. The method further includes: generating a layout data indicating a layout of the semiconductor integrated circuit, based on a cell-based design technique. The method further includes: referring to the generated layout data to extract the parameter associated with a target cell included in the semiconductor integrated circuit; and calculating a delay value of the target cell by using the extracted parameter and the delay function.

Abstract: A method of designing a semiconductor integrated circuit includes: generating a layout data indicating a layout; and generating a mask data based on the layout data. The generating the mask data includes: referring to the layout data to extract a parameter that specifies a layout pattern around a target transistor included in the semiconductor integrated circuit, wherein the parameter includes at least a width of a device isolation structure around the target transistor; correcting a gate length and a gate width of the target transistor to offset a variation of a characteristic of the target transistor from a design value, the variation depending on the extracted parameter; and generating the mask data from the layout data in which the gate length and the gate width are corrected.