Patents by Inventor Kentaro Kumazawa

Kentaro Kumazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230311509
    Abstract: A coating head includes: a plurality of nozzles; a plurality of pressure chambers communicating with the plurality of nozzles; an ink flow path communicating with the plurality of pressure chambers; and a coating layer that is at least partially provided on liquid contact surfaces of the plurality of nozzles, the plurality of pressure chambers, and the ink flow path.
    Type: Application
    Filed: March 13, 2023
    Publication date: October 5, 2023
    Inventors: KENTARO KUMAZAWA, SHUHEI NAKATANI, KAZUNOBU IRIE, FUTOSHI OHTSUKA, YOUSUKE TOYOFUKU
  • Patent number: 11279133
    Abstract: The ink jet device is provided with a plurality of ink jet heads including a plurality of nozzles disposed linearly with each other at intervals in a predetermined longitudinal direction and ejecting ink in different regions each other in the printing width direction; and a position adjusting mechanism performing rotating operation of changing the intervals in the printing width direction of the nozzles by rotating the plurality of ink jet heads around an axis perpendicular to the print surface of the print object, and performing a shifting operation of shifting at least one of the plurality of ink jet heads in the printing width direction.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: March 22, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hidehiro Yoshida, Yousuke Toyofuku, Kentaro Kumazawa
  • Publication number: 20210094293
    Abstract: The ink jet device is provided with a plurality of ink jet heads including a plurality of nozzles disposed linearly with each other at intervals in a predetermined longitudinal direction and ejecting ink in different regions each other in the printing width direction; and a position adjusting mechanism performing rotating operation of changing the intervals in the printing width direction of the nozzles by rotating the plurality of ink jet heads around an axis perpendicular to the print surface of the print object, and performing a shifting operation of shifting at least one of the plurality of ink jet heads in the printing width direction.
    Type: Application
    Filed: September 22, 2020
    Publication date: April 1, 2021
    Applicant: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Hidehiro YOSHIDA, Yousuke TOYOFUKU, Kentaro KUMAZAWA
  • Patent number: 10369783
    Abstract: A high precision printing method taking into consideration the variance in the thickness of a printing target. An ink-jet printing method, including: (i) measuring a distance between a printing target and at least one nozzle; (ii) measuring a flying speed and a flying angle of an ink(a) discharged from the at least one nozzle; (iii) printing a test substrate with an ink to identify a location on which an ink(b) is spotted, and calculating a thickness-related displacement that is a displacement from the location on which the ink is spotted, based on a thickness difference between the printing target and the test substrate from results obtained in Step (i), and the flying speed and the flying angle of the ink(a) obtained in Step (ii); and (iv) discharging an ink(c) from the at least one nozzle to achieve actual printing of the printing target with the ink(c) while correcting the thickness-related displacement.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: August 6, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Kentaro Kumazawa, Shuhei Nakatani, Takao Nagumo, Takashi Inoue, Futoshi Ohtsuka
  • Publication number: 20180222180
    Abstract: A high precision printing method taking into consideration the variance in the thickness of a printing target. An ink-jet printing method, including: (i) measuring a distance between a printing target and at least one nozzle; (ii) measuring a flying speed and a flying angle of an ink(a) discharged from the at least one nozzle; (iii) printing a test substrate with an ink to identify a location on which an ink(b) is spotted, and calculating a thickness-related displacement that is a displacement from the location on which the ink is spotted, based on a thickness difference between the printing target and the test substrate from results obtained in Step (i), and the flying speed and the flying angle of the ink(a) obtained in Step (ii); and (iv) discharging an ink(c) from the at least one nozzle to achieve actual printing of the printing target with the ink(c) while correcting the thickness-related displacement.
    Type: Application
    Filed: February 1, 2018
    Publication date: August 9, 2018
    Inventors: KENTARO KUMAZAWA, SHUHEI NAKATANI, TAKAO NAGUMO, TAKASHI INOUE, FUTOSHI OHTSUKA
  • Patent number: 8895359
    Abstract: A semiconductor chip (1) is flip-chip mounted on a circuit board (4) with an underfill resin (6) interposed between the semiconductor chip (1) and the circuit board (4) and a container covering the semiconductor chip (1) is bonded on the circuit board (4). At this point, the semiconductor chip (1) positioned with the underfill resin (6) interposed between the circuit board (4) and the semiconductor chip (1) is pressed and heated by a pressure-bonding tool (8); meanwhile, the surface of the underfill resin (6) protruding around the semiconductor chip (1) is pressed by the pressure-bonding tool (8) through a film (13) on which a surface unevenness is formed in a periodically repeating pattern, so that a surface unevenness (16a) is formed. The inner surface of the container covering the semiconductor chip (1) is bonded to the surface unevenness (16a) on the surface of the underfill resin.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: November 25, 2014
    Assignee: Panasonic Corporation
    Inventors: Yoshihiro Tomura, Kazumichi Shimizu, Kentaro Kumazawa
  • Patent number: 8436253
    Abstract: A mounting structure is provided which includes an electronic component; a circuit board; a first insulating resin and a second insulating resin which are placed between the electronic component and the circuit board, for sealing; a plurality of bumps are formed on the electronic component or the circuit board; a plurality of counter electrodes of the circuit board or the electronic component, connected to the plurality of bumps; and a plurality of joining regions. The plurality of joining regions are formed by the second insulating resin, a plurality of first insulating resin regions are disposed around the joining regions so that the joining regions are sandwiched by the plurality of first insulating resin regions, the first insulating resin and the second insulating resin each contain filler, and the second insulating resin has a higher curing temperature than the curing temperature of the first insulating resin.
    Type: Grant
    Filed: March 23, 2009
    Date of Patent: May 7, 2013
    Assignee: Panasonic Corporation
    Inventors: Takayuki Higuchi, Yoshihiro Tomura, Kazuhiro Nobori, Kentaro Kumazawa
  • Patent number: 8426965
    Abstract: While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. Entire side faces at corner portions of the semiconductor chip are covered with the seal-bonding resin. Therefore, loads generated at the corner portions due to board flexures for thermal expansion and contraction differences among the individual members caused by heating and cooling during mounting as well as for mechanical loads after mounting so that internal breakdown of the semiconductor chip can be avoided.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: April 23, 2013
    Assignee: Panasonic Corporation
    Inventors: Teppei Iwase, Yoshihiro Tomura, Kazuhiro Nobori, Yuichiro Yamada, Kentaro Kumazawa
  • Patent number: 8415794
    Abstract: A semiconductor device includes a semiconductor element having a plurality of element electrodes formed thereon, a circuit board having board electrodes respectively corresponding to the element electrodes formed thereon and having the semiconductor element mounted thereon, and bumps each of which is provided on at least one of the element electrode and the board electrode, and connects together the element electrode and the board electrode corresponding to each other when the semiconductor element is mounted on the circuit board. Furthermore, at least one of a dielectric layer and a resistive layer is provided between at least one of the bumps and the element or board electrode on which the at least one of the bumps is provided, so that the element or board electrode, the dielectric layer or the resistive layer, and the bump form a parallel-plate capacitor or electrical resistance.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: April 9, 2013
    Assignee: Panasonic Corporation
    Inventors: Kentaro Kumazawa, Yoshihiro Tomura
  • Patent number: 8358018
    Abstract: An electronic component, in which the outer perimeter portion of a component (2) is surrounded with a first sealing resin (4), a second sealing resin (3) is filled within the periphery of the first sealing resin (4), the component (2) and a board (1) are electrically connected by a wire (5), the edge, in the vicinity of which the wire (5) passes, of the outer perimeter edge portions of the component (2) is formed to be a chamfered oblique surface (31), and the wire (5) is provided to extend to the board (1) along the oblique surface (31). By this means, the overall height of the electronic component can be kept low.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: January 22, 2013
    Assignee: Panasonic Corporation
    Inventors: Makoto Imanishi, Yoshihiro Tomura, Kentaro Kumazawa
  • Publication number: 20120298310
    Abstract: While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. Entire side faces at corner portions of the semiconductor chip are covered with the seal-bonding resin. Therefore, loads generated at the corner portions due to board flexures for thermal expansion and contraction differences among the individual members caused by heating and cooling during mounting as well as for mechanical loads after mounting so that internal breakdown of the semiconductor chip can be avoided.
    Type: Application
    Filed: August 6, 2012
    Publication date: November 29, 2012
    Inventors: Teppei IWASE, Yoshihiro Tomura, Kazuhiro Nobori, Yuichiro Yamada, Kentaro Kumazawa
  • Patent number: 8264079
    Abstract: While bumps formed on pads of a semiconductor chip and a board having a sheet-like seal-bonding resin stuck on its surface are set face to face, the bumps and the board are pressed to each other with a tool, thereby forming a semiconductor chip mounted structure in which the seal-bonding resin is filled between the semiconductor chip and the board and in which the pads of the semiconductor chip and the electrodes of the board are connected to each other via the bumps, respectively. Entire side faces at corner portions of the semiconductor chip are covered with the seal-bonding resin. Therefore, loads generated at the corner portions due to board flexures for thermal expansion and contraction differences among the individual members caused by heating and cooling during mounting as well as for mechanical loads after mounting so that internal breakdown of the semiconductor chip can be avoided.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: September 11, 2012
    Assignee: Panasonic Corporation
    Inventors: Teppei Iwase, Yoshihiro Tomura, Kazuhiro Nobori, Yuichiro Yamada, Kentaro Kumazawa
  • Patent number: 8163599
    Abstract: A flip-chip mounting apparatus has a shield film (18) on the side of a pressurizing film (10b) of a tool protection sheet (10). When a semiconductor chip (1) is heated and pressurized via the tool protection sheet (10), the pressurizing film (10b) is released from a mold by a sheet fixing jig (9), and is expanded by a pressurizing/heating tool (11) to abut against an insulating resin film (5) protruding from the periphery of the semiconductor chip (1) and cure the insulating resin film (5) with an external pressure being applied.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: April 24, 2012
    Assignee: Panasonic Corporation
    Inventors: Yoshihiro Tomura, Kentaro Kumazawa, Takayuki Higuchi, Koujiro Nakamura
  • Patent number: 8080884
    Abstract: A mounting structure of the present invention includes a semiconductor element 101, a circuit board 301 having electrodes 302 opposed to electrodes 102 of the semiconductor element 101, and conductive two-layer bumps 213. Second bumps 210 joined to the electrodes 302 of the circuit board 301 are formed larger than first bumps 209 joined to the electrodes 102 of the semiconductor element 101. The axis of the first bump 209 and the axis of the second bump 210 are not aligned with each other.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: December 20, 2011
    Assignee: Panasonic Corporation
    Inventors: Kojiro Nakamura, Yoshihiro Tomura, Kentaro Kumazawa
  • Patent number: 8050049
    Abstract: The present invention provides a semiconductor device of a double-side mounting structure including a circuit board and a plurality of semiconductor chips arranged and joined together on the opposite surfaces of the circuit board, wherein in an area in which the semiconductor chip 31 mounted on the top surface of the circuit board 2 overlaps with the semiconductor chip 32 mounted on the bottom surface of the circuit board 2, a recess portion 21 (or a protruding portion 22) is formed in the surfaces of the circuit board 2.
    Type: Grant
    Filed: April 21, 2009
    Date of Patent: November 1, 2011
    Assignee: Panasonic Corporation
    Inventors: Teppei Iwase, Kazuhiro Nobori, Yoshihiro Tomura, Koujiro Nakamura, Kentaro Kumazawa
  • Patent number: 8035225
    Abstract: A semiconductor chip dual-sided assembly which has a higher degree of reliability of connections between semiconductor chips and a circuit substrate is realized. This is achieved by the assembly including a plurality of upper side pads (2a) provided on a substrate upper surface (1a); a plurality of lower side pads (2b) provided on a substrate lower surface (1b) corresponding to the upper side pads (2a) across the substrate (1), respectively; a first semiconductor chip (4) having first bumps (8a) joined to the upper side pads (2a), respectively; and a second semiconductor chip (5) having second bumps (8b) joined to the lower side pads (2b), respectively.
    Type: Grant
    Filed: December 28, 2005
    Date of Patent: October 11, 2011
    Assignee: Panasonic Corporation
    Inventors: Kojiro Nakamura, Hidenobu Nishikawa, Kentaro Kumazawa
  • Patent number: 7994638
    Abstract: In this semiconductor chip 3, a table electrode 13 is interposed between a bump electrode 14 and an electrode pad 6. The table electrode 13 is formed by forming a plurality of cores 15 having a smaller Young's modulus than the bump electrode 14, on the electrode pad 6, and then covering the surfaces of the cores 15 with a conductive electrode 16. When the semiconductor chip 3 is flip-chip mounted, the bump electrode 14 is plastically deformed and the table electrode 13 is elastically deformed appropriately, thereby obtaining a good conductive state.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: August 9, 2011
    Assignee: Panasonic Corporation
    Inventors: Yoshihiro Tomura, Kazuhiro Nobori, Yuichiro Yamada, Kentaro Kumazawa, Teppei Iwase
  • Patent number: 7985078
    Abstract: The electrode junction structure includes: a glass substrate; a plurality of flexible substrates, in a planar view, arranged to cross over an edge of the glass substrate and arranged to have a space from each other along the edge; an adhesive for joining the glass substrate and each flexible substrate; and a sealing resin for covering junction portions between the glass substrate and each flexible substrate, wherein an edge of the sealing resin is formed so that the edge of the sealing resin has, in the planar view, a consecutive waveform portion in which a convex portion and a concave portion alternate with an imaginary line as a center axis, the imaginary line being parallel to the edge of the glass substrate and locating outer than the edge of the glass substrate, and wherein the convex portions are formed to be located on the flexible substrates.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: July 26, 2011
    Assignee: Panasonic Corporation
    Inventors: Kentaro Kumazawa, Masahiro Ono, Yoshihiro Tomura
  • Publication number: 20110175237
    Abstract: A semiconductor chip (1) is flip-chip mounted on a circuit board (4) with an underfill resin (6) interposed between the semiconductor chip (1) and the circuit board (4) and a container covering the semiconductor chip (1) is bonded on the circuit board (4). At this point, the semiconductor chip (1) positioned with the underfill resin (6) interposed between the circuit board (4) and the semiconductor chip (1) is pressed and heated by a pressure-bonding tool (8); meanwhile, the surface of the underfill resin (6) protruding around the semiconductor chip (1) is pressed by the pressure-bonding tool (8) through a film (13) on which a surface unevenness is formed in a periodically repeating pattern, so that a surface unevenness (16a) is formed. The inner surface of the container covering the semiconductor chip (1) is bonded to the surface unevenness (16a) on the surface of the underfill resin.
    Type: Application
    Filed: November 6, 2009
    Publication date: July 21, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Yoshihiro Tomura, Kazumichi Shimizu, Kentaro Kumazawa
  • Patent number: 7910406
    Abstract: An electronic circuit device includes at least one semiconductor element, a plurality of external connection terminals, connecting conductors electrically connecting the semiconductor element and external connection terminals, and an insulating resin covering the semiconductor element and supporting the connecting conductors integrally. The semiconductor element is buried in the insulating resin, and terminal surfaces of the external connection terminals are exposed from the insulating resin.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: March 22, 2011
    Assignee: Panasonic Corporation
    Inventors: Kentaro Kumazawa, Shigeru Kondou, Hidenobu Nishikawa