Patents by Inventor Kentaro SUGAYA

Kentaro SUGAYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240154039
    Abstract: A semiconductor device includes a transistor including, a first to fifth insulator, a first to third oxide, a first to third conductor. An opening reaching the second oxide is provided in the fourth insulator and the fifth insulator. The third oxide, the third insulator, and the third conductor are arranged sequentially from the inner wall side of the opening so as to fill the opening. In the channel length direction of the transistor, at least part of the fourth insulator in a region where the fourth insulator and the second oxide do not overlap with each other is in contact with the first insulator. In the channel width direction of the transistor, at least part of the third oxide in a region where the third oxide and the second oxide do not overlap with each other is in contact with the first insulator.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 9, 2024
    Inventors: Shunpei YAMAZAKI, Katsuaki TOCHIBAYASHI, Ryota HODO, Kentaro SUGAYA, Naoto YAMADE
  • Patent number: 11962202
    Abstract: A motor includes a shaft, a rotor, a stator including a coil and opposed to the rotor, and a bearing configured to support the shaft. In addition, the motor further includes a first temperature sensor disposed farther toward an outer periphery side than the coil, and a second temperature sensor disposed farther toward an inner periphery side than the coil.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: April 16, 2024
    Assignee: MINEBEA MITSUMI Inc.
    Inventors: Kouji Kebukawa, Kentaro Suzuki, Wataru Nogamida, Yoshihisa Okabuchi, Takayuki Sugaya, Takahiro Saito
  • Publication number: 20240088232
    Abstract: A semiconductor device that can be scaled down or highly integrated is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer and the second layer each include a transistor. The transistor in the first layer and the transistor in the second layer each include a first oxide, a first conductor and a second conductor over the first oxide, a first insulator placed to cover the first conductor, the second conductor, and the first oxide, a second insulator over the first insulator, a second oxide placed between the first conductor and the second conductor over the first oxide, a third insulator over the second oxide, a third conductor over the third insulator, and a fourth insulator in contact with a top surface of the second insulator, a top surface of the second oxide, a top surface of the third insulator, and a top surface of the third conductor.
    Type: Application
    Filed: November 22, 2023
    Publication date: March 14, 2024
    Inventors: Kosei NEI, Tsutomu MURAKAWA, Toshihiko TAKEUCHI, Kentaro SUGAYA
  • Patent number: 11881513
    Abstract: A semiconductor device that can be scaled down or highly integrated is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer and the second layer each include a transistor. The transistor in the first layer and the transistor in the second layer each include a first oxide, a first conductor and a second conductor over the first oxide, a first insulator placed to cover the first conductor, the second conductor, and the first oxide, a second insulator over the first insulator, a second oxide placed between the first conductor and the second conductor over the first oxide, a third insulator over the second oxide, a third conductor over the third insulator, and a fourth insulator in contact with a top surface of the second insulator, a top surface of the second oxide, a top surface of the third insulator, and a top surface of the third conductor.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: January 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kosei Nei, Tsutomu Murakawa, Toshihiko Takeuchi, Kentaro Sugaya
  • Patent number: 11869979
    Abstract: A semiconductor device includes a transistor including, a first to fifth insulator, a first to third oxide, a first to third conductor. An opening reaching the second oxide is provided in the fourth insulator and the fifth insulator. The third oxide, the third insulator, and the third conductor are arranged sequentially from the inner wall side of the opening so as to fill the opening. In the channel length direction of the transistor, at least part of the fourth insulator in a region where the fourth insulator and the second oxide do not overlap with each other is in contact with the first insulator. In the channel width direction of the transistor, at least part of the third oxide in a region where the third oxide and the second oxide do not overlap with each other is in contact with the first insulator.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: January 9, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Katsuaki Tochibayashi, Ryota Hodo, Kentaro Sugaya, Naoto Yamade
  • Patent number: 11817507
    Abstract: A semiconductor device having a high on-state current is provided. The semiconductor device includes a first oxide; a first conductor and a second conductor provided over the first oxide to be separated from each other; and a second oxide provided over the first oxide and between the first conductor and the second conductor. Each of the first oxide and the second oxide has crystallinity, the first oxide includes a region where a c-axis is aligned substantially perpendicularly to a top surface of the first oxide, and the second oxide includes a region where the c-axis is aligned substantially perpendicularly to the top surface of the first oxide, a region where the c-axis is aligned substantially perpendicularly to a side surface of the first conductor, and a region where the c-axis is aligned substantially perpendicularly to a side surface of the second conductor.
    Type: Grant
    Filed: February 9, 2022
    Date of Patent: November 14, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tsutomu Murakawa, Hiroki Komagata, Katsuaki Tochibayashi, Kentaro Sugaya
  • Publication number: 20230200198
    Abstract: To provide a light-emitting element in which an organic compound layer can be processed at once by a photolithography technique. A first electrode and an organic compound layer including an electron-injection layer are formed over an insulating surface. The electron-injection layer is the outermost layer of the organic compound layer and contains an organic compound having a basic skeleton and an acid dissociation constant pKa of greater than or equal to 1. A sacrificial layer and a mask are formed over the electron-injection layer and the sacrificial layer is processed into an island shape using the mask. With use of the island-shaped sacrificial layer as a mask, the organic compound layer is processed into an island shape to cover the first electrode. Part of the island-shaped sacrificial layer is removed with an acidic chemical solution to expose the electron-injection layer. A second electrode is formed to cover the electron-injection layer.
    Type: Application
    Filed: December 13, 2022
    Publication date: June 22, 2023
    Inventors: Shunpei YAMAZAKI, Sachiko KAWAKAMI, Nobuharu OHSAWA, Yuji IWAKI, Ryota HODO, Kentaro SUGAYA, Shinya SASAGAWA, Takahiro FUJIE, Yoshikazu HIURA, Toshiki SASAKI, Takeyoshi WATABE, Kunihiko SUZUKI
  • Publication number: 20230047805
    Abstract: A semiconductor device with a high on-state current is provided. An oxide semiconductor film; a source electrode and a drain electrode over the oxide semiconductor film; an interlayer insulating film positioned to cover the oxide semiconductor film, the source electrode, and the drain electrode; a gate insulating film over the oxide semiconductor film; a barrier insulating film over the oxide semiconductor film; and a gate electrode over the gate insulating film are included. The barrier insulating film is positioned between the source electrode and the gate insulating film and between the drain electrode and the gate electrode. An opening is formed in the interlayer insulating film so as to overlap with a region between the source electrode and the drain electrode. The barrier insulating film, the gate insulating film, and the gate electrode are positioned in the opening of the interlayer insulating film.
    Type: Application
    Filed: January 7, 2021
    Publication date: February 16, 2023
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Ryota HODO, Katsuaki TOCHIBAYASHI, Kentaro SUGAYA
  • Publication number: 20220271169
    Abstract: A semiconductor device having a high on-state current is provided. The semiconductor device includes a first oxide; a first conductor and a second conductor provided over the first oxide to be separated from each other; and a second oxide provided over the first oxide and between the first conductor and the second conductor. Each of the first oxide and the second oxide has crystallinity, the first oxide includes a region where a c-axis is aligned substantially perpendicularly to a top surface of the first oxide, and the second oxide includes a region where the c-axis is aligned substantially perpendicularly to the top surface of the first oxide, a region where the c-axis is aligned substantially perpendicularly to a side surface of the first conductor, and a region where the c-axis is aligned substantially perpendicularly to a side surface of the second conductor.
    Type: Application
    Filed: February 9, 2022
    Publication date: August 25, 2022
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Tsutomu MURAKAWA, Hiroki KOMAGATA, Katsuaki TOCHIBAYASHI, Kentaro SUGAYA
  • Publication number: 20220271168
    Abstract: A semiconductor device with a small variation in transistor characteristics is provided. The semiconductor device includes an oxide semiconductor, a first conductor and a second conductor over the oxide semiconductor, a first insulator in contact with a top surface of the first conductor, a second insulator in contact with a top surface of the second conductor, a third insulator which is positioned over the first insulator and the second insulator and has an opening overlapping with a region between the first conductor and the second conductor, a fourth insulator positioned over the oxide semiconductor and in the region between the first conductor and the second conductor, and a third conductor over the fourth insulator. Each of the first insulator and the second insulator is a metal oxide including an amorphous structure.
    Type: Application
    Filed: July 13, 2020
    Publication date: August 25, 2022
    Inventors: Shunpei YAMAZAKI, Shinya SASAGAWA, Ryota HODO, Takashi HIROSE, Yoshihiro KOMATSU, Katsuaki TOCHIBAYASHI, Kentaro SUGAYA
  • Patent number: 11417773
    Abstract: A semiconductor device with favorable reliability is provided. The semiconductor device includes a first oxide, a second oxide, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor is provided in contact with a top surface of the first oxide. The second conductor is provided in contact with the top surface of the first oxide. The first insulator is provided over the first conductor and the second conductor. The second oxide is provided in contact with the top surface of the first oxide. The second insulator is provided over the second oxide. The third conductor is provided over the second insulator. The first insulator has a function of inhibiting diffusion of oxygen. The first oxide includes indium, an element M (M is gallium, yttrium, or tin), and zinc. The first oxide includes a first region overlapping with the third conductor.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: August 16, 2022
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Erika Takahashi, Hiroaki Honda, Kentaro Sugaya, Shinya Sasagawa
  • Publication number: 20220246765
    Abstract: A semiconductor device includes a transistor including, a first to fifth insulator, a first to third oxide, a first to third conductor. An opening reaching the second oxide is provided in the fourth insulator and the fifth insulator. The third oxide, the third insulator, and the third conductor are arranged sequentially from the inner wall side of the opening so as to fill the opening. In the channel length direction of the transistor, at least part of the fourth insulator in a region where the fourth insulator and the second oxide do not overlap with each other is in contact with the first insulator. In the channel width direction of the transistor, at least part of the third oxide in a region where the third oxide and the second oxide do not overlap with each other is in contact with the first insulator.
    Type: Application
    Filed: April 22, 2022
    Publication date: August 4, 2022
    Inventors: Shunpei YAMAZAKI, Katsuaki TOCHIBAYASHI, Ryota HODO, Kentaro SUGAYA, Naoto YAMADE
  • Publication number: 20220199832
    Abstract: A semiconductor device with small variations in transistor characteristics is provided. The semiconductor device includes an oxide; a first conductor and a second conductor provided apart from each other over the oxide; an insulator in a region between the first conductor and the second conductor over the oxide; and a conductor over the insulator. A side surface of the oxide, a top surface of the first conductor, a side surface of the first conductor, a top surface of the second conductor, and a side surface of the second conductor include regions in contact with a nitride containing silicon.
    Type: Application
    Filed: May 12, 2020
    Publication date: June 23, 2022
    Inventors: Shunpei YAMAZAKI, Ryota HODO, Katsuaki TOCHIBAYASHI, Hiroaki HONDA, Kentaro SUGAYA
  • Patent number: 11316051
    Abstract: A semiconductor device includes a transistor including, a first to fifth insulator, a first to third oxide, a first to third conductor. An opening reaching the second oxide is provided in the fourth insulator and the fifth insulator. The third oxide, the third insulator, and the third conductor are arranged sequentially from the inner wall side of the opening so as to fill the opening. In the channel length direction of the transistor, at least part of the fourth insulator in a region where the fourth insulator and the second oxide do not overlap with each other is in contact with the first insulator. In the channel width direction of the transistor, at least part of the third oxide in a region where the third oxide and the second oxide do not overlap with each other is in contact with the first insulator.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: April 26, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Katsuaki Tochibayashi, Ryota Hodo, Kentaro Sugaya, Naoto Yamade
  • Patent number: 11257959
    Abstract: A semiconductor device having a high on-state current is provided. The semiconductor device includes a first oxide; a first conductor and a second conductor provided over the first oxide to be separated from each other; and a second oxide provided over the first oxide and between the first conductor and the second conductor. Each of the first oxide and the second oxide has crystallinity, the first oxide includes a region where a c-axis is aligned substantially perpendicularly to a top surface of the first oxide, and the second oxide includes a region where the c-axis is aligned substantially perpendicularly to the top surface of the first oxide, a region where the c-axis is aligned substantially perpendicularly to a side surface of the first conductor, and a region where the c-axis is aligned substantially perpendicularly to a side surface of the second conductor.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: February 22, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Tsutomu Murakawa, Hiroki Komagata, Katsuaki Tochibayashi, Kentaro Sugaya
  • Publication number: 20220020881
    Abstract: A semiconductor device having favorable electrical characteristics is provided.
    Type: Application
    Filed: November 21, 2019
    Publication date: January 20, 2022
    Inventors: Shunpei YAMAZAKI, Kentaro SUGAYA, Ryota HODO, Kenichiro MAKINO, Shuhei NAGATSUKA
  • Patent number: 11133420
    Abstract: A semiconductor device with high on-state current is provided.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 28, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Iida, Ryota Hodo, Kentaro Sugaya, Ryu Komatsu, Toshiya Endo, Shunpei Yamazaki
  • Publication number: 20210242345
    Abstract: A semiconductor device with favorable reliability is provided. The semiconductor device includes a first oxide, a second oxide, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor is provided in contact with a top surface of the first oxide. The second conductor is provided in contact with the top surface of the first oxide. The first insulator is provided over the first conductor and the second conductor. The second oxide is provided in contact with the top surface of the first oxide. The second insulator is provided over the second oxide. The third conductor is provided over the second insulator. The first insulator has a function of inhibiting diffusion of oxygen. The first oxide includes indium, an element M (M is gallium, yttrium, or tin), and zinc. The first oxide includes a first region overlapping with the third conductor.
    Type: Application
    Filed: May 14, 2019
    Publication date: August 5, 2021
    Inventors: Shunpei YAMAZAKI, Erika TAKAHASHI, Hiroaki HONDA, Kentaro SUGAYA, Shinya SASAGAWA
  • Publication number: 20210167174
    Abstract: A semiconductor device that can be scaled down or highly integrated is provided. The semiconductor device includes a first layer and a second layer over the first layer. The first layer and the second layer each include a transistor. The transistor in the first layer and the transistor in the second layer each include a first oxide, a first conductor and a second conductor over the first oxide, a first insulator placed to cover the first conductor, the second conductor, and the first oxide, a second insulator over the first insulator, a second oxide placed between the first conductor and the second conductor over the first oxide, a third insulator over the second oxide, a third conductor over the third insulator, and a fourth insulator in contact with a top surface of the second insulator, a top surface of the second oxide, a top surface of the third insulator, and a top surface of the third conductor.
    Type: Application
    Filed: April 16, 2019
    Publication date: June 3, 2021
    Inventors: Kosei NEI, Tsutomu MURAKAWA, Toshihiko TAKEUCHI, Kentaro SUGAYA
  • Publication number: 20200388710
    Abstract: A semiconductor device includes a transistor including, a first to fifth insulator, a first to third oxide, a first to third conductor. An opening reaching the second oxide is provided in the fourth insulator and the fifth insulator. The third oxide, the third insulator, and the third conductor are arranged sequentially from the inner wall side of the opening so as to fill the opening. In the channel length direction of the transistor, at least part of the fourth insulator in a region where the fourth insulator and the second oxide do not overlap with each other is in contact with the first insulator. In the channel width direction of the transistor, at least part of the third oxide in a region where the third oxide and the second oxide do not overlap with each other is in contact with the first insulator.
    Type: Application
    Filed: February 21, 2019
    Publication date: December 10, 2020
    Inventors: Shunpei YAMAZAKI, Katsuaki TOCHIBAYASHI, Ryota HODO, Kentaro SUGAYA, Naoto YAMADE