Patents by Inventor Kenya Kawano

Kenya Kawano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11652023
    Abstract: Provided is a highly reliable semiconductor device capable of reducing stress generated in a semiconductor element even when a highly elastic joining material such as a Pb-free material is used in a power semiconductor having a double-sided mounting structure. The semiconductor device includes a semiconductor element including a gate electrode only on one surface, an upper electrode connected to the surface of the semiconductor element on which the gate electrode is provided, and a lower electrode connected to a surface opposite to the surface of the semiconductor element on which the gate electrode is provided.
    Type: Grant
    Filed: October 23, 2020
    Date of Patent: May 16, 2023
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Naoki Takeda, Tomohiro Onda, Kenya Kawano, Hiroshi Shintani, Yu Harubeppu, Hisashi Tanie
  • Publication number: 20210143081
    Abstract: Provided is a highly reliable semiconductor device capable of reducing stress generated in a semiconductor element even when a highly elastic joining material such as a Pb-free material is used in a power semiconductor having a double-sided mounting structure. The semiconductor device includes a semiconductor element including a gate electrode only on one surface, an upper electrode connected to the surface of the semiconductor element on which the gate electrode is provided, and a lower electrode connected to a surface opposite to the surface of the semiconductor element on which the gate electrode is provided.
    Type: Application
    Filed: October 23, 2020
    Publication date: May 13, 2021
    Inventors: Naoki TAKEDA, Tomohiro ONDA, Kenya KAWANO, Hiroshi SHINTANI, Yu HARUBEPPU, Hisashi TANIE
  • Patent number: 10304761
    Abstract: Provided are a semiconductor device realized easily at low cost without requiring a complicated manufacturing process, and an alternator using the same. The semiconductor device includes a base having a base seat, a lead having a lead header, and an electronic circuit body, wherein the electronic circuit body is arranged between the base and the lead; the base seat is connected to a first surface of the electronic circuit body; the lead header is connected to a second surface of the electronic circuit body; the electronic circuit body is integrally covered by resin, including a transistor circuit chip having a switching element, a control circuit chip for controlling the switching element, a drain frame, and a source frame; either one of the drain frame and the source frame, and the base are connected; and the other one of the drain frame and the source frame, and the lead are connected.
    Type: Grant
    Filed: November 17, 2016
    Date of Patent: May 28, 2019
    Assignee: Hitachi Power Semiconductor Device, Ltd.
    Inventors: Kenya Kawano, Tetsuya Ishimaru, Shinichi Kurita, Takeshi Terakawa
  • Publication number: 20170141018
    Abstract: Provided are a semiconductor device realized easily at low cost without requiring a complicated manufacturing process, and an alternator using the same. The semiconductor device includes a base having a base seat, a lead having a lead header, and an electronic circuit body, wherein the electronic circuit body is arranged between the base and the lead; the base seat is connected to a first surface of the electronic circuit body; the lead header is connected to a second surface of the electronic circuit body; the electronic circuit body is integrally covered by resin, including a transistor circuit chip having a switching element, a control circuit chip for controlling the switching element, a drain frame, and a source frame; either one of the drain frame and the source frame, and the base are connected; and the other one of the drain frame and the source frame, and the lead are connected.
    Type: Application
    Filed: November 17, 2016
    Publication date: May 18, 2017
    Inventors: Kenya KAWANO, Tetsuya ISHIMARU, Shinichi KURITA, Takeshi TERAKAWA
  • Patent number: 9142479
    Abstract: Provided is an electronic device having a semiconductor device and a mounting board. The semiconductor device has a die pad, a semiconductor chip on the die pad, a coupling member coupling the die pad to the semiconductor chip, and a semiconductor package member covering the upper portion of the semiconductor chip and the side surface of the die pad. In this semiconductor device, the plane area of the coupling member coupling the mounting board to the die pad is smaller than the plane area of the lower surface of the die pad exposed from the semiconductor package material. This makes it possible to reduce separation between the die pad and the semiconductor chip resulting from cracks, due to temperature cycling, of the coupling member present between the die pad and the semiconductor chip.
    Type: Grant
    Filed: August 22, 2013
    Date of Patent: September 22, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Kenya Kawano, Hiroyuki Nakamura, Yukihiro Sato
  • Patent number: 8763242
    Abstract: In a method of manufacturing a semiconductor device, a second wiring substrate is stacked over a first wiring substrate using a conductive paste, where each wiring substrate has mounted thereon an electronic component. The conductive paste is hardened to form a metal column which forms an electrical connection between the first wiring substrate and the second wiring substrate. The wiring substrates are sealed with a resin. The semiconductor device can be downsized, thinned, and made highly reliable, and its manufacturing cost can be reduced. By using conductive paste for the electrical connection between the wiring substrates, a connecting pitch can be smaller than that in a connecting method of using a solder ball including Cu core, and a connection at low temperature can be achieved. Also, by coating the conductive paste by a print-coating or dispense-coating method, manufacturing is simplified and the manufacturing cost is reduced.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: July 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kenya Kawano, Chiko Yorita, Yuji Shirai
  • Publication number: 20140061821
    Abstract: Provided is an electronic device having a semiconductor device and a mounting board. The semiconductor device has a die pad, a semiconductor chip on the die pad, a coupling member coupling the die pad to the semiconductor chip, and a semiconductor package member covering the upper portion of the semiconductor chip and the side surface of the die pad. In this semiconductor device, the plane area of the coupling member coupling the mounting board to the die pad is smaller than the plane area of the lower surface of the die pad exposed from the semiconductor package material. This makes it possible to reduce separation between the die pad and the semiconductor chip resulting from cracks, due to temperature cycling, of the coupling member present between the die pad and the semiconductor chip.
    Type: Application
    Filed: August 22, 2013
    Publication date: March 6, 2014
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenya KAWANO, Hiroyuki NAKAMURA, Yukihiro SATO
  • Publication number: 20130067424
    Abstract: A life prediction method of an electronic device in which the life prediction accuracy is more improved than that in a related art technique, and a design method of an electronic device based on the above method, are established. Life prediction is performed by incorporating either of a change in a physical property of a solder joint portion and a change in the fatigue life of a solder, the changes occurring when left at a high temperature. The change in a physical property of the solder joint portion or the change in the fatigue life of the solder is determined from the relationship between a heat treatment temperature and a heat treatment time. These changes are then formulated to be incorporated into the life prediction.
    Type: Application
    Filed: August 23, 2012
    Publication date: March 14, 2013
    Inventors: Kenichi YAMAMOTO, Ryosuke Kimoto, Kenya Kawano, Hisashi Tanie, Yasuhiro Naka
  • Publication number: 20110156274
    Abstract: The present invention provides a semiconductor device capable of suppressing degradation in connection reliability due to the decrease in thickness of a conductive adhesive caused by the movement of a connecting plate in a semiconductor device to which a power transistor is mounted. A step is provided in the thin part of the connecting plate connected to a lead post to lock the connecting plate by contacting the step to the tip of the lead post. Alternatively, a groove is provided in the thin part of the connecting plate to lock the connecting plate by connecting the lead post to only the part of the connecting plate on the tip side from the groove.
    Type: Application
    Filed: March 8, 2011
    Publication date: June 30, 2011
    Applicant: Renesas Technology Corp.
    Inventors: Kenya Kawano, Kisho Ashida, Naotaka Tanaka, Hiroshi Sato, Ichio Shimizu
  • Publication number: 20110128713
    Abstract: In a semiconductor device in which a plurality of wiring substrates each mounting an electronic component are stacked and sealed by a resin, the semiconductor device can be downsized, thinned, and highly reliable, and its manufacturing cost can be reduced. By using a metal paste for electrical connection between the stacked lower-layer side wiring substrate and upper-layer side wiring substrate, a connecting pitch can be smaller than that in a connecting method of using a solder ball including Cu core, and the connection at low temperature can be achieved. Also, by coating a metal paste by a print-coating method or a dispense-coating method, manufacturing steps are simplified, so that the manufacturing cost is reduced.
    Type: Application
    Filed: November 30, 2010
    Publication date: June 2, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Kenya KAWANO, Chiko YORITA, Yuji SHIRAI
  • Publication number: 20100181628
    Abstract: Prevention of disconnection of a bonding wire resulting from adhesive interface delamination between a resin and a leadframe, and improvement of joint strength of the resin and the leadframe are achieved in a device manufactured by a low-cost and simple processing. A boss is provided on a source lead by a stamping processing, and a support pillar is provided in a concave portion on a rear side of the source lead in order to prevent ultrasonic damping upon joining the bonding wire onto the boss, so that an insufficiency of the joint strength between the bonding wire and the source lead is prevented. Also, a continuous bump is provided on the boss so as to surround a joint portion between the source lead and the bonding wire, so that disconnection of the bonding wire resulting from delamination between the resin and the source lead is prevented.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 22, 2010
    Applicant: Renesas Technology Corp.
    Inventors: Kenya Kawano, Kisho Ashida, Kuniharu Muto, Ichio Shimizu, Tomibumi Inoue
  • Patent number: 7732919
    Abstract: Coupling reliability of a passive component is improved to increase the reliability of a semiconductor device. A first through hole is formed in a first electrode part of a first plate-like lead, and a second through hole is formed in a second electrode part of a second plate-like lead. As a result, at the first electrode part of the first plate-like lead, one external terminal of the passive component can be coupled to the first electrode parts on both sides of the first through hole while being laid across the first through hole. Also, at the second electrode part of the second plate-like lead, the other external terminal of the passive component can be coupled to the second electrode parts on both sides of the second through hole while being laid across the second through hole. Accordingly, at central portions both in the longitudinal and width directions of the passive component, the passive component is surrounded by sealing members.
    Type: Grant
    Filed: January 29, 2009
    Date of Patent: June 8, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Ichio Shimizu, Kenya Kawano, Kisho Ashida, Yuichi Machida
  • Patent number: 7692296
    Abstract: A semiconductor device is provided with connection reliability between a bump electrode and a substrate electrode. An elastic modulus of an adhesive material used to electrically connect a metal bump and an interconnect pattern, and sealing the circuit surface of an LSI chip, after thermosetting is Ea; an elastic modulus of an insulating material of a packaging substrate surface layer after thermosetting is Eb; an elastic modulus of a core material, if used, is Ec, and the following rational expression is satisfied at normal temperature or a thermal contact bonding temperature of the adhesive material: at least Ea<Eb<Ec, preferably ?Eb<Ea<Eb<3Ea(<Ec). With this arrangement, a stable connection state can be attained irrespective of the level of the contact bonding load or fluctuations of it upon mass production and, therefore, high yield can be attained at low cost.
    Type: Grant
    Filed: March 22, 2005
    Date of Patent: April 6, 2010
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Naotaka Tanaka, Kenya Kawano, Akira Nagai, Koji Tasaki, Masaaki Yasuda
  • Patent number: 7656030
    Abstract: Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: February 2, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Yasuo Osone, Kenya Kawano, Chiko Yorita, Yu Hasegawa, Yuji Shirai, Naotaka Tanaka, Seiichi Tomoi, Hiroshi Okabe
  • Publication number: 20090190320
    Abstract: Coupling reliability of a passive component is improved to increase the reliability of a semiconductor device. A first through hole is formed in a first electrode part of a first plate-like lead, and a second through hole is formed in a second electrode part of a second plate-like lead. As a result, at the first electrode part of the first plate-like lead, one external terminal of the passive component can be coupled to the first electrode parts on both sides of the first through hole while being laid across the first through hole. Also, at the second electrode part of the second plate-like lead, the other external terminal of the passive component can be coupled to the second electrode parts on both sides of the second through hole while being laid across the second through hole. Accordingly, at central portions both in the longitudinal and width directions of the passive component, the passive component is surrounded by sealing members.
    Type: Application
    Filed: January 29, 2009
    Publication date: July 30, 2009
    Inventors: ICHIO SHIMIZU, Kenya Kawano, Kisho Ashida, Yuichi Machida
  • Patent number: 7554193
    Abstract: A semiconductor device capable of reducing the thermal resistance in a flip chip packaging structure while achieving both the high radiation performance and manufacturing readiness without increasing the manufacturing cost is provided. In a semiconductor device having a semiconductor circuit for power amplification and a control circuit of the semiconductor circuit laminated on a multilayer circuit board, the semiconductor circuit for power amplification and the control circuit are aligned in parallel on the same semiconductor element, and the semiconductor element is flip-chip connected on the multilayer circuit board. Further, a second semiconductor element mounted in addition to the first semiconductor element and all components and submodules are flip-chip connected. Also, a plurality of bumps are united in order to improve the radiation performance and thermal vias of the multilayer circuit board are formed in second and lower layers of the wiring layers in the multilayer circuit board.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: June 30, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Yasuo Osone, Chiko Yorita, Kenya Kawano, Yu Hasegawa, Yuji Shirai, Seiichi Tomoi, Tsuneo Endou, Satoru Konishi, Hirokazu Nakajima
  • Patent number: 7432594
    Abstract: A semiconductor device has a semiconductor chip including first and second surfaces opposed to each other in a thickness direction of the semiconductor chip, wherein the first and second surfaces include first and second electrode surfaces respectively, and first and second electrically conductive members covering the first and second electrode surfaces respectively as seen in the thickness direction to be electrically connected to the first and second electrode surfaces respectively.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: October 7, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kisho Ashida, Akira Muto, Ichio Shimizu, Toshiyuki Hata, Kenya Kawano, Naotaka Tanaka, Nae Hisano
  • Publication number: 20080224282
    Abstract: A technique for preventing cracks and residual resin on a semiconductor chip in a molding process in the assembly of semiconductor devices is provided. A distance from a bottom surface of a cavity of a lower mold die to a ceiling surface of a cavity of an upper mold die of a resin molding die is made same as or smaller than a distance from a lower surface of a die pad to an upper surface of a plate terminal, and an U-shape elastic body is arranged on semiconductor elements between the plate terminal and the die pad, thereby mitigating a load due to a clamp pressure of mold dies in the molding process by an elastic deformation of the elastic body. Consequently, a load applied on the semiconductor devices is reduced, thereby preventing formation of cracks on the semiconductor elements.
    Type: Application
    Filed: January 25, 2008
    Publication date: September 18, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Kisho Ashida, Kenya Kawano, Akira Muto, Ichio Shimizu
  • Publication number: 20070176266
    Abstract: The present invention provides a semiconductor device capable of suppressing degradation in connection reliability due to the decrease in thickness of a conductive adhesive caused by the movement of a connecting plate in a semiconductor device to which a power transistor is mounted. A step is provided in the thin part of the connecting plate connected to a lead post to lock the connecting plate by contacting the step to the tip of the lead post. Alternatively, a groove is provided in the thin part of the connecting plate to lock the connecting plate by connecting the lead post to only the part of the connecting plate on the tip side from the groove.
    Type: Application
    Filed: December 15, 2006
    Publication date: August 2, 2007
    Applicant: Renesas Technology Corp.
    Inventors: Kenya Kawano, Kisho Ashida, Naotaka Tanaka, Hiroshi Sato, Ichio Shimizu
  • Publication number: 20070176298
    Abstract: Heating elements different in heat generating timing are laminated in a stacked state, and the heating element close to a wiring substrate is allowed to function as a heat diffusion plate for another heating element.
    Type: Application
    Filed: January 10, 2007
    Publication date: August 2, 2007
    Applicants: Hitachi, Ltd., Renesas Technology Corp.
    Inventors: Yasuo Osone, Kenya Kawano, Chiko Yorita, Yu Hasegawa, Yuji Shirai, Naotaka Tanaka, Seiichi Tomoi, Hiroshi Okabe