Abstract: A conductivity modulation type MOSFET (IGBT) including an n-type high resistance layer, p-type base regions selectively formed in a first major surface of the high resistance layer, n-type source regions formed in the surface of each base region, a p.sup.+ well region formed in a central region of each of the base regions, a channel in the base region between one of the n-type source regions and the high resistance layer, a gate electrode formed above the channel, an emitter electrode formed in contact with the p.sup.+ well region and the n-type source region, a gate insulating film formed between the gate electrode and the channel, and a metal electrode formed in contact with a second major surface of the high resistance layer opposite the first major source, the electrode forming a Schottky barrier junction.

Abstract: A conductivity modulation type MOSFET including a first region of a first conductivity type having a low impurity concentration, second regions of a second conductivity type selectively formed on the surface region of one side of the first region, third regions of the first conductivity type selectively formed on the surface region of the second regions, gate electrodes each formed above the surface region of the second region located between the first region and the third region, a plurality of gate insulating films interlayered between the gate electrodes and the surface region of the second regions, an emitter electrode in contact with both the second regions and the third regions, a fourth region of the second conductivity type having a high impurity concentration, formed adjoining to another side of the first region, fifth regions of the second conductivity type, selectively formed surrounding the fourth region, having a lower impurity concentration than that of the fourth region, and a collector electro

Abstract: A conductivity modulation type MOSFET including a first region of a first conductivity type having a low impurity concentration, second regions of a second conductivity type selectively formed on the surface region of one side of the first region, third regions of the first conductivity type selectively formed on the surface region of the second regions, gate electrodes each formed above the surface region of the second region located between the first region and the third region, a plurality of gate insulating films interlayered between the gate electrodes and the surface region of the second regions, an emitter electrode in contact with both the second regions and the third regions, a fourth region of the second conductivity type having a high impurity concentration, formed adjoining to another side of the first region, fifth regions of the second conductivity type, selectively formed surrounding the fourth region, having a lower impurity concentration than that of the fourth region, and a collector electro

Abstract: When bypassing a high voltage surge by externally installing a diode between a collector and a gate and protecting a circuit by turning on an IGBT, it is difficult to select a withstand voltage of the diode, because the withstand voltage of the IGBT must be higher with a certain margin. In the present invention, regions of an inverse conductivity type are formed in a high resistivity layer of an IGBT as in base region, and a transistor is formed together with a collector layer of an inverse conductivity type, which is connected between the collectors of an IGBT to be utilized as a clamping transistor. The breakdown voltage of this transistor is made lower than the breakdown voltage of a bipolar transistor of the IGBT main body. Then when the transistor breaks down, the gate-emitter capacity of the IGBT is charged and the IGBT is turned on, thus absorbing the high energy produced by an abnormal voltage into the chip and increasing the withstand capacity.

Abstract: A MOS semiconductor device having a surge protecting circuit comprising a semiconductor substrate having a major surface, a plurality of electrodes overlying the major surface, a MOS circuit in the major surface, and a bidirectional semiconductor surge absorber coupled between the gate of the MOS circuit and a reference electrode contacting the major surface of the substrate. In another embodiment, the MOS semiconductor device further comprises a bidirectional Zener diode connected in series with the bidirectional semiconductor surge absorber.

Abstract: A conductivity modulation type MOSFET including a first region of a first conductivity type having a low impurity concentration, second regions of a second conductivity type selectively formed on the surface region of one side of the first region, third regions of the first conductivity type selectively formed on the surface region of the second regions, gate electrodes each formed above the surface region of the second region located between the first region and the third region, a plurality of gate insulating films interlayered between the gate electrodes and the surface region of the second regions, an emitter electrode in contact with both the second regions and the third regions, a fourth region of the second conductivity type having a high impurity concentration, formed adjoining to another side of the first region, fifth regions of the second conductivity type, selectively formed surrounding the fourth region, having a lower impurity concentration than that of the fourth region, and a collector electro

Abstract: This invention relates to an insulated gate type semiconductor device having an increased breakdown endurance capacity. According to the present invention, by decreasing the space between base regions or increasing the widths of adjacent base regions of cells near a connecting conductor fixed portion of a common emitter electrode of an IGBT or a common source electrode of an insulated gate type MOSFET so that the ratio between both falls within the range of 0.2 to 0.4, it is possible to suppress the latch-up phenomenon or the latch-back phenomenon which is liable to occur because of a local temperature rise caused by concentration of electric current. Furthermore, it is possible to limit the increase of the forward voltage drop in that case to within a range that does not inhibit practical use of the device . With this, either latch-up endurance capacity, in the case of a IGBT, or latch-back endurance capacity, in the case of an insulated gate type MOSFET, is improved.

Abstract: A metal oxide semiconductor device comprising a semiconductor substrate having a semiconductor layer of a first conductivity type disposed thereon. A plurality of first regions of a second conductivity type are disposed on and embedded in a first surface of the semiconductor layer of the first conductivity type, and a plurality of second regions of the first conductivity type disposed on the first surface of the semiconductor layer between said first regions.

Abstract: A single mask method for providing multiple masking patterns, using excess etching techniques, which is usable for developing a semiconductor substrate for a semiconductor device which results in an increased current being required before latchup occurs in the semiconductor device.

Abstract: The present invention relates to a method of producing a metal-oxide semiconductor device with improved capacity for preventing an actuation of a parasitic bipolar transistor. In the present invention, a metal-oxide seminconductor device is produced through a process in which a single conductive semiconductor region with low-impurity density, on top of which region a gate electrode is provided via a gate-insulating film, consists of two sub-layers with different specific resistance. The upper sub-layer of the region has a significantly lower specific resistance than the lower sub-layer of the region. When a lifetime-reducing agent for reducing the reverse-recovery time of a built-in diode is diffused into the single conductive semiconductor region with low-impurity density, the lifetime-reducing agent concentrates in the upper sub-layer of the region, thereby increasing the specific resistance of the upper sub-layer.

Abstract: The present invention relates to a metal-oxide-semiconductor device containing a plurality of units on one semiconductor substrate. The device has a high impurity concentration region of the same conductivity type as a base layer formed near each corner of a source layer and provides improved current capacity in power applications. The high impurity concentration regions reduce a diffusion resistance in the vicinity of the corners of the source layer, thereby improving resistance of each unit to breakdown under electrical stress.