Abstract: There is provided a magnesium alloy containing mass percent Al: 5% to 7%, Ca: 2% to 4%, Mn: 0.1% to 0.8%, Sr: 0.001% to 0.05% and rare earth elements: 0.1% to 0.6%. If necessary, an allowable content is set in each of Si, Zn, Cu, Ni, Fe and Cl of the unavoidable impurities, with Si not higher than mass percent 0.01%, Zn not higher than mass percent 0.01%, Cu not higher than mass percent 0.008%, Ni not higher than mass percent 0.001%, Fe not higher than mass percent 0.004%, and Cl not higher than mass percent 0.003%. There is also provided a magnesium alloy member injected in the die by using such an alloy.

Abstract: There is provided a magnesium alloy containing mass percent Al: 5% to 7%, Ca: 2% to 4%, Mn: 0.1% to 0.8%, Sr: 0.001% to 0.05% and rare earth elements: 0.1% to 0.6%. If necessary, an allowable content is set in each of Si, Zn, Cu, Ni, Fe and Cl of the unavoidable impurities, with Si not higher than mass percent 0.01%, Zn not higher than mass percent 0.01%, Cu not higher than mass percent 0.008%, Ni not higher than mass percent 0.001%, Fe not higher than mass percent 0.004%, and Cl not higher than mass percent 0.003%. There is also provided a magnesium alloy member injected in the die by using such an alloy.

Abstract: A semiconductor memory device is disclosed for use in writing and reading data. The memory device is provided with a memory cell array including a plurality of word lines, a plurality of bit lines, and a plurality of memory cells connected to each of the word lines and bit lines, respectively. The memory device is provided with a precharger which precharges to set the potential of each bit line to a given level before the data on the memory cells can be read out onto the bit lines. The memory device is responsive to an address signal, and a controller for controlling the precharger. The controller activates the precharger so that all the bit lines are precharged when a previously selected word line changes following the change of the address signal.

Abstract: A first selector outputs either an output of an ALU (arithmetic logic unit) or a first clipped value to a first bus. A temporary register holds the output signal of the ALU, and a second selector outputs either the output signal of the temporary register or a second clipped value. A controller causes an operation result regarding lower data of first and second operands to be stored in the temporary register in a first cycle of the ALU when each of the first and second operands consists of 2n bits while the ALU operates on n bits per cycle thereof. When an operation result regarding upper data of the first and second operands overflows in a second cycle of the ALU, the controller causes the first and second selectors to output the first and second clipped values. When the operation result regarding the upper data does not overflow, the controller causes the first and second selector to respectively output the output signals of the ALU and the temporary register.

Abstract: An analog-to-digital converter comprising one or more charging and discharging circuits (C.sub.A and/or C.sub.B), a control circuit (6' and/or 6"), and a timer-counter (7). The control circuit performs the discharging operation alternately and continuously on the charging and discharging circuits. The timer-counter counts a predetermined number of times the discharging operation is performed so as to create a digital value (T).