Abstract: A refresh switching circuit for a dynamic RAM which is capable of easily switching a RAS-only refresh to a CAS-before-RAS refresh, thereby consuming less electric power, easily executing a shift to a self-refresh (suspending), and obtaining comparability with conventional personal computer systems. The dynamic RAM comprises a CPU (101), dynamic RAM arrays (115) and a system logic (110) for use in a microprocessor system, and further comprises a refresh switching circuit (111) for switching the RAS-only refresh to the CAS-before-RAS refresh.

Abstract: A character signal including sixteen binary coded signal blocks each with an additional bit is stored in a closed loop memory and displayed, as corresponding characters on a display. In response to the display, a student strikes keys on a keyboard to deliver signal blocks, similar in coded form to the stored ones, to a comparator where they are successively compared with corresponding stored signal blocks. Upon the correct striking of the keys, the comparator applies a coincidence signal to the memory to change the value of the additional bit to erase the associated displayed character. Upon incorrect striking of the keys the changed bit is changed back to the original value to again display all the characters on the display.